On the Tracking Performance of a Galileo/GPS Receiver based on Hybrid FPGA+DSP Board

The design of receivers in the field of Global Navigation Satellite Systems (GNSS) is going through a fundamental stage of development. As a matter of fact, the market is showing the need of having user terminals with improved performance, and able to match the requirements of different services and applications related to positioning. On the other hand, the constant advancements on the way leading to the modernization of the actual Global Positioning System (GPS) and the development of the new European Satellite System, Galileo, are driving the design of new architectures for the future GNSS receivers able to manage signals with high sampling rates. Considering this framework, the solution of developing such user terminals on reconfigurable platforms has grown in importance. From the manufacturers point of view, such an approach will make possible to upgrade and reconfigure the system with new features, while from the research point of view it will make easier to perform tests on signal processing algorithms for the new modulation schemes foreseen by the future GNSS signal requirements. In this light, this paper introduces a work for the realization of a test receiver based on Field Programmable Gate Arrays (FPGAs) and Digital Signal Processors (DSPs), design according to the Software Defined Radio (SDR) philosophy. The test receiver assure a 100% level of flexibility for each one of its functional blocks. Starting from the justification for the hardware tools selected, the paper reports the last results about the analysis of the system performance going through the details of the architecture description, focusing the attention on the Code and Carrier Tracking Loops. Since the new Galileo modulated Signah-In-Space (SIS) are not yet available, a software version of an input signal generator has been realised, and its realization will be discussed taking care of the real-time constraints. Results of the Tracking Jitter Error (TJE) for various modulation schemes implemented on the described architecture are presented, comparing them with simulative results.