This paper describes implementation details of a hardware compression and decompression unit (CDU) for optimizing energy consumption in processor-based systems. Many algorithms for data compression (i.e., profile-driven, adaptive, differential) have been introduced in [1, 2]. In all cases, data compression and decompression are performed on-the-fly on the cache-to-memory path: Uncompressed cache lines are compressed before they are written back to main memory, and decompressed when cache refills occur. This paper completes and extends the contributions of [1, 2] by providing evidence on the feasibility of the proposed compression architectures by specifically addressing hardware implementation issues. CDU design is targeted towards energy minimization in the cache- bus-memory subsystem with a strict constraint on performance. As a result, average memory energy reductions evaluated on several benchmark programs are around 24%, at no performance penalty.

Hardware Implementation of Data Compression Algorithms for Memory Energy Optimization / Benini, L; Bruni, D; Macii, Alberto; Macii, Enrico. - (2003), pp. 250-251. (Intervento presentato al convegno ISVLSI-03: IEEE International Symposium on VLSI Systems tenutosi a Tampa, FL) [10.1109/ISVLSI.2003.1183487].

Hardware Implementation of Data Compression Algorithms for Memory Energy Optimization

MACII, Alberto;MACII, Enrico
2003

Abstract

This paper describes implementation details of a hardware compression and decompression unit (CDU) for optimizing energy consumption in processor-based systems. Many algorithms for data compression (i.e., profile-driven, adaptive, differential) have been introduced in [1, 2]. In all cases, data compression and decompression are performed on-the-fly on the cache-to-memory path: Uncompressed cache lines are compressed before they are written back to main memory, and decompressed when cache refills occur. This paper completes and extends the contributions of [1, 2] by providing evidence on the feasibility of the proposed compression architectures by specifically addressing hardware implementation issues. CDU design is targeted towards energy minimization in the cache- bus-memory subsystem with a strict constraint on performance. As a result, average memory energy reductions evaluated on several benchmark programs are around 24%, at no performance penalty.
2003
0769519040
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1500008
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