This paper presents the realization of an energy-aware system-on-chip that implements the baseband processing as well as the medium access control and data link control functionalities of a 5 GHz wireless system. It is compliant with the HIPERLAN/2 standard, but it also covers critical functionality of the IEEE 802.11a standard. Two embedded processor cores, dedicated hardware, on-chip memory elements, as well as advanced bus architectures and peripheral inter-faces were carefully combined and optimized for the targeted application, leading to a proper trade-off of silicon area, flexibility and power consumption. A system-level low-power design methodology has been used, due to the fact that power consumption is the most critical parameter in electronic portable system design. The 17.5 million-transistor solution was implemented in a 0.18 μm CMOS pro-cess and performs baseband processing at data rates up to 54 Mbit/s, with average power consumption of about 550 mW.
Energy-aware system-on-chip for 5 GHz wireless LANs / Bisdounis, L; Blionas, S; Macii, Enrico; Nikolaidis, S; Zafalon, R.. - 3728:(2005), pp. 166-176. (Intervento presentato al convegno 15th International Workshop, PATMOS 2005 tenutosi a Leuven nel September 21-23, 2005) [10.1007/11556930_18].
Energy-aware system-on-chip for 5 GHz wireless LANs
MACII, Enrico;
2005
Abstract
This paper presents the realization of an energy-aware system-on-chip that implements the baseband processing as well as the medium access control and data link control functionalities of a 5 GHz wireless system. It is compliant with the HIPERLAN/2 standard, but it also covers critical functionality of the IEEE 802.11a standard. Two embedded processor cores, dedicated hardware, on-chip memory elements, as well as advanced bus architectures and peripheral inter-faces were carefully combined and optimized for the targeted application, leading to a proper trade-off of silicon area, flexibility and power consumption. A system-level low-power design methodology has been used, due to the fact that power consumption is the most critical parameter in electronic portable system design. The 17.5 million-transistor solution was implemented in a 0.18 μm CMOS pro-cess and performs baseband processing at data rates up to 54 Mbit/s, with average power consumption of about 550 mW.Pubblicazioni consigliate
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
https://hdl.handle.net/11583/1500103
Attenzione
Attenzione! I dati visualizzati non sono stati sottoposti a validazione da parte dell'ateneo