Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs

Item Type: Proceeding
MIUR type: Proceedings > Proceedings
Title: Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs
Authors string: Sithambaram P.; Macii A.; Macii E.
University authors:
Page Range: pp. 477-487
Journal or Publication Title: LECTURE NOTES IN COMPUTER SCIENCE
Publisher: Springer
ISBN: 9783540290131
ISSN: 0302-9743
Volume: 3728
Event Title: 15th International Workshop, PATMOS 2005
Event Location: Leuven (BEL)
Event Dates: September 21-23, 2005
Abstract: Memory partitioning has proved to be a promising solution to reduce energy consumption in complex SoCs. Memory partitioning comes in different flavors, depending on the specific domain of usage and design constraints to be met. In this paper, we consider a technique that allows us to customize the architecture of physically partitioned SRAM macros according to the given application to be executed. We present design solutions for the various components of the partitioned memory architecture, and develop a memory generator for automatically generating layouts and schematics of the optimized memory macros. Experimental results, collected for two different case studies, demonstrate the efficiency of the architecture and the usability of the prototype memory generator. In fact, the achieved energy savings w.r.t. implementations featuring monolithic architectures, are around 43% for a memory macro of 1KByte, and around 45% for a memory macro of 8KByte
Date: 2005
Status: Published
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Departments (original): DAUIN - Control and Computer Engineering
Departments: DAUIN - Department of Control and Computer Engineering
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    Subjects: Area 09 - Ingegneria industriale e dell'informazione > SISTEMI DI ELABORAZIONE DELLE INFORMAZIONI
    Date Deposited: 23 Jan 2007 14:01
    Last Modified: 24 Oct 2014 11:28
    Id Number (DOI): 10.1007/11556930_49
    Permalink: http://porto.polito.it/id/eprint/1500551
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