Memory partitioning has proved to be a promising solution to reduce energy consumption in complex SoCs. Memory partitioning comes in different flavors, depending on the specific domain of usage and design constraints to be met. In this paper, we consider a technique that allows us to customize the architecture of physically partitioned SRAM macros according to the given application to be executed. We present design solutions for the various components of the partitioned memory architecture, and develop a memory generator for automatically generating layouts and schematics of the optimized memory macros. Experimental results, collected for two different case studies, demonstrate the efficiency of the architecture and the usability of the prototype memory generator. In fact, the achieved energy savings w.r.t. implementations featuring monolithic architectures, are around 43% for a memory macro of 1KByte, and around 45% for a memory macro of 8KByte.

Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs / Sithambaram, P.; Macii, Alberto; Macii, Enrico. - 3728:(2005), pp. 477-487. (Intervento presentato al convegno 15th International Workshop, PATMOS 2005 tenutosi a Leuven (BEL) nel September 21-23, 2005) [10.1007/11556930_49].

Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs

MACII, Alberto;MACII, Enrico
2005

Abstract

Memory partitioning has proved to be a promising solution to reduce energy consumption in complex SoCs. Memory partitioning comes in different flavors, depending on the specific domain of usage and design constraints to be met. In this paper, we consider a technique that allows us to customize the architecture of physically partitioned SRAM macros according to the given application to be executed. We present design solutions for the various components of the partitioned memory architecture, and develop a memory generator for automatically generating layouts and schematics of the optimized memory macros. Experimental results, collected for two different case studies, demonstrate the efficiency of the architecture and the usability of the prototype memory generator. In fact, the achieved energy savings w.r.t. implementations featuring monolithic architectures, are around 43% for a memory macro of 1KByte, and around 45% for a memory macro of 8KByte.
2005
9783540290131
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/1500551
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