ARPIA: a High-Level Evolutionary Test Signal Generator

Item Type: Proceeding
MIUR type: Proceedings > Proceedings
Title: ARPIA: a High-Level Evolutionary Test Signal Generator
Authors string: Corno F; Cumani G; Sonza Reorda M; Squillero G.
University authors:
Page Range: pp. 298-306
Journal or Publication Title: LECTURE NOTES IN COMPUTER SCIENCE
Referee type: Not specified type
Publisher: Springer
ISBN: 3540419209
ISSN: 0302-9743
Volume: 2037
Event Title: EvoWorkshops 2001: EvoCOP, EvoFlight, EvoIASP, EvoLearn, and EvoSTIM
Event Location: Como (ITA)
Event Dates: April 18–20, 2001
Abstract: The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective fault models and test signals generators are still missing. This paper proposes ARPIA, a new simulation-based evolutionary test generator. ARPIA adopts an innovative high-level fault model that enables efficient fault simulation and guarantees good correlation with gate-level results. The approach exploits an evolutionary algorithm to drive the search of effective patterns within the gigantic space of all possible signal sequences. ARPIA operates on register-transfer level VHDL descriptions and generates effective test patterns. Experimental results show that the achieved results are comparable or better than those obtained by high-level similar approaches or even by gate-level ones
Date: 2001
Status: Published
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Uncontrolled Keywords:
Departments (original): DAUIN - Control and Computer Engineering
Departments: DAUIN - Department of Control and Computer Engineering
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    Subjects: Area 09 - Ingegneria industriale e dell'informazione > SISTEMI DI ELABORAZIONE DELLE INFORMAZIONI
    Date Deposited: 27 Mar 2007 13:03
    Last Modified: 16 Oct 2013 03:41
    Id Number (DOI): 10.1007/3-540-45365-2_31
    Permalink: http://porto.polito.it/id/eprint/1501661
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