Automatic Validation of Protocol Interfaces Described in VHDL

Item Type: Proceeding
MIUR type: Proceedings > Proceedings
Title: Automatic Validation of Protocol Interfaces Described in VHDL
Authors string: Corno F; Sonza Reorda M; Squillero G.
University authors:
Page Range: pp. 205-213
Referee type: Not specified type
Publisher: Springer
ISBN: 3540673539
ISSN: 0302-9743
Volume: 1803
Event Title: EvoWorkshops 2000: EvoIASP, EvoSCONDI, EvoTel, EvoSTIM, EvoRob, and EvoFlight
Event Location: Edinburgh (GBR)
Event Dates: April 17, 2000
Abstract: In present days, most of the design activity is performed at a high level of abstraction, thus designers need to be sure that their designs are syntactically and semantically correct before starting the automatic synthesis process. The goal of this paper is to propose an automatic input pattern generation tool able to assist designers in the generation of a test bench for difficult parts of small- or medium- sized digital protocol interfaces. The proposed approach exploit a Genetic Algorithm connected to a commercial simulator for cultivating a set of input sequence able to execute given statements in the interface description. The proposed approach has been evaluated on the new ITC'99 benchmark set, a collection of circuits offering a wide spectrum of complexity. Experimental results show that some portions of the circuits remained uncovered, and the subsequent manual analysis allowed identifying design redundancies
Date: 2000
Status: Published
Language of publication:
Uncontrolled Keywords:
Departments (original): DAUIN - Control and Computer Engineering
Departments: DAUIN - Department of Control and Computer Engineering
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    Date Deposited: 27 Mar 2007 13:57
    Last modification data (IRIS): 15 Oct 2013 12:55:43
    Update date (PORTO): 24 Oct 2014 14:43
    Id Number (DOI): 10.1007/3-540-45561-2_20
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