Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating

The use of sleep transistors as power-gating elements to cut-off sub-threshold leakage stand-by currents has become a very popular solution to tackle the rise of leakage energy consumption in nano-CMOS designs. One of the most critical challenges in sleep-transistor based power gating is the sizing of the sleep transistor, which mainly depends on the discharge current pattern over time of the set of cells that share a single sleep transistor. In this work we provide a sleep transistor clustering and sizing methodology that improves over previous solutions by (i) accounting for sleep transistor area constraints (thus implying the possibility of gating only a subset of the cells of the design), and (ii) by utilizing the temporal variations in discharge current pattern to achieve improved leakage power-savings. Experimental results on standard benchmarks show that we can achieve improvement in leakage power savings, compared to previous works, ranging from 12% to 17% on average, depending on the allowed area constraint.