Timing driven placement for fault tolerant circuits implemented on SRAM-based FPGAs

Full text not available from this repository. Send a request to the author for a copy of the paper
Item Type: Proceeding
MIUR type: Proceedings > Proceedings
Title: Timing driven placement for fault tolerant circuits implemented on SRAM-based FPGAs
Authors string: Sterpone L.
University authors:
Page Range: pp. 85-96
Journal or Publication Title: LECTURE NOTES IN COMPUTER SCIENCE
Referee type: Not specified type
Publisher: Springer
ISSN: 0302-9743
Volume: 5453
Event Title: 5th International Workshop, ARC 2009
Event Location: Karlsruhe (Germany)
Event Dates: March 16-18, 2009
Abstract: Electronic systems for safety critical applications such as space and avionics need the maximum level of dependability for guarantee the success of their missions. Contrariwise the computation capabilities required in these fields are constantly increasing for afford the implementation of different kind of applications ranging from the signal processing to the networking. SRAM-based FPGA is the candidate device for achieve this goal thanks to their high versatility of implementing complex circuits with a very short development time. However, in critical environments, the presence of Single Event Upsets (SEUs) affecting the FPGA's functionalities, requires the adoption of specific fault tolerant techniques, like Triple Modular Redundancy (TMR), able to increase the protection capability against radiation effects, but on the other side, introducing a dramatic penalty in terms of performances. In this paper, it is proposed a new timing-driven placement algorithm for implementing soft-errors resilient circuits on SRAM-based FPGAs with a negligible degradation of performance. The algorithm is based on a placement heuristic able to remove the crossing error domains while decreasing the routing congestions and delay inserted by the TMR routing and voting scheme. Experimental analysis performed by timing analysis and SEU static analysis point out a performance improvement of 29% on the average with respect to standard TMR approach and an increased robustness against SEU affecting the FPGA's configuration memory
Date: 2009
Status: Published
Language of publication: English
Uncontrolled Keywords:
Departments (original): DAUIN - Control and Computer Engineering
Departments: DAUIN - Department of Control and Computer Engineering
Related URLs:
    Subjects:
    Date Deposited: 21 Dec 2009 11:12
    Last Modified: 27 Oct 2014 14:14
    Id Number (DOI): 10.1007/978-3-642-00641-8_11
    Permalink: http://porto.polito.it/id/eprint/1894241
    Linksolver URL: Linksolver link
    Citations:

    This field presents the citations number present on Scopus and Web of Science databases e links to the remote records. Also Google Scholar link is present.

    There may be discrepancies with respect to the data in databases for the following reasons:

    • Differences from fields (title, year,...) in UGOV and those in the databases.
    • PORTO citations are extracted monthly. The db is in real time
    • The WoS citation number reflect the collections subscribed by Politecnico (Science citation index Expanded and Conference Proceedings Citation Index)

    For informations contact scrivia/porto

    +
    -

    Actions (login required)

    View Item View Item