The continues improvement of manufacturing technologies allows the realization of integrated circuits containing an ever increasing number of transistors. A major part of these devices is devoted to realize SRAM blocks. Test and diagnosis of SRAM circuits are therefore an important challenge for improving quality of next generation integrated circuits. This paper proposes a flexible platform for testing and diagnosis of SRAM circuits. The architecture is based on the use of a low cost FPGA based board allowing high diagnosability while keeping costs at a very low level.

A Low-Cost FPGA-Based Test and Diagnosis Architecture for SRAMs / DI CARLO, Stefano; Prinetto, Paolo Ernesto; Scionti, A.; Figueras, J.; Manch, S.; Rodriguez Montanes, R.. - STAMPA. - (2009), pp. 141-146. (Intervento presentato al convegno IEEE First International Conference on Advances in System Testing and Validation Lifecycle (VALID) tenutosi a Lisbon, PT nel 20-25 Sept. 2009) [10.1109/VALID.2009.29].

A Low-Cost FPGA-Based Test and Diagnosis Architecture for SRAMs

DI CARLO, STEFANO;PRINETTO, Paolo Ernesto;
2009

Abstract

The continues improvement of manufacturing technologies allows the realization of integrated circuits containing an ever increasing number of transistors. A major part of these devices is devoted to realize SRAM blocks. Test and diagnosis of SRAM circuits are therefore an important challenge for improving quality of next generation integrated circuits. This paper proposes a flexible platform for testing and diagnosis of SRAM circuits. The architecture is based on the use of a low cost FPGA based board allowing high diagnosability while keeping costs at a very low level.
2009
9781424448623
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2286561
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