Digital filters implement a continuos computation and therefore generally they do not exhibit any structural idleness. This can prevent the usage of classical low-power optimizations that exploit idleness, such as clock gating. In this work, we propose a data-driven implementation of clock gating for digital filters, which relies on the observation that often times the dynamic range of the inputs uses only a small portion of the bidwith, resulting in most of the higher-order bits of the registers having very low switching activity. When this occurs, unused bits in each filter tap can be clock-gated; since all the gated flip-flops share the same idle condition (i.e., new and currently stored are identical) they can share a single clock gating cell. The number of flip-flops that can be gated with a single cell depends on the tradeoff between the power saved and the performance penalty. This technique has been applied on a digital filter used within an ultra low-power industrial design; comparison with other standard and advanced automatic clock-gating methods highlights the effectiveness of the proposed technique.

Data-Driven Clock Gating for Digital Filters / Bonanno, Alberto; Bocca, Alberto; Macii, Alberto; Macii, Enrico; Poncino, Massimo. - 5953:(2010), pp. 96-105. (Intervento presentato al convegno 19th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2009) tenutosi a Delft (NL) nel September 9-11, 2009) [10.1007/978-3-642-11802-9_14].

Data-Driven Clock Gating for Digital Filters

BONANNO, ALBERTO;BOCCA, ALBERTO;MACII, Alberto;MACII, Enrico;PONCINO, MASSIMO
2010

Abstract

Digital filters implement a continuos computation and therefore generally they do not exhibit any structural idleness. This can prevent the usage of classical low-power optimizations that exploit idleness, such as clock gating. In this work, we propose a data-driven implementation of clock gating for digital filters, which relies on the observation that often times the dynamic range of the inputs uses only a small portion of the bidwith, resulting in most of the higher-order bits of the registers having very low switching activity. When this occurs, unused bits in each filter tap can be clock-gated; since all the gated flip-flops share the same idle condition (i.e., new and currently stored are identical) they can share a single clock gating cell. The number of flip-flops that can be gated with a single cell depends on the tradeoff between the power saved and the performance penalty. This technique has been applied on a digital filter used within an ultra low-power industrial design; comparison with other standard and advanced automatic clock-gating methods highlights the effectiveness of the proposed technique.
2010
9783642118012
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2298485
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