Early Power Estimation for System-on-Chip Designs

Item Type: Proceeding
MIUR type: Proceedings > Proceedings
Title: Early Power Estimation for System-on-Chip Designs
Authors string: M. Lajolo; L. Lavagno; M. Sonza Reorda; M. Violante
University authors:
Page Range: pp. 108-117
Publisher: Springer
ISBN: 3540410686
ISSN: 0302-9743
Volume: 1918
Event Title: Power and Timing Modeling, Optimization and Simulation 10th International Workshop, PATMOS 2000
Event Location: Göttingen (DEU)
Event Dates: Sep. 13-15, 2000
Abstract: Reduction of chip packaging and cooling costs for deep sub-micron System-On-Chip (SOC) designs is an emerging issue. We present a simulationbased methodology able to realistically model the complex environment in which a SOC design operates in order to provide early and accurate power consumption estimation. We show that a rich functional test bench provided by a designer with a deep knowledge of a complex system is very often not appropriate for power analysis and can lead to power estimation errors of some orders of magnitude. To address this issue, we propose an automatic input sequence generation approach based on a heuristic algorithm able to upgrade a set of test vectors provided by the designer. The obtained sequence closely reflects the worst-case power consumption for the chip and allows looking at how the chip is going to work over time
Date: 2000
Status: Published
Language of publication: English
Uncontrolled Keywords:
Departments (original): DAUIN - Control and Computer Engineering
Departments: DAUIN - Department of Control and Computer Engineering
DET - Department of Electronics and Telecommunications
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    Date Deposited: 13 Oct 2010 18:31
    Last modification data (IRIS): 04 Feb 2016 12:03:58
    Update date (PORTO): 06 Feb 2016 03:52
    Id Number (DOI): 10.1007/3-540-45373-3_11
    Permalink: http://porto.polito.it/id/eprint/2374680
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