The use of model checking in ATPG for sequential circuits

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Item Type: Proceeding
MIUR type: Proceedings > Proceedings
Title: The use of model checking in ATPG for sequential circuits
Authors string: P. Camurati, M. Gilli, P. Prinetto, M. Sonza Reorda
University authors:
Page Range: pp. 86-95
Referee type: Not specified type
Publisher: Springer
ISBN: 3540544771
ISSN: 0302-9743
Volume: 531
Event Title: Computer-Aided Verification 2nd International Conference, CAV '90
Event Location: New Brunswick, NJ (USA)
Event Dates: June 18-21, 1990
Abstract: Some design environments may prevent Design for Testability techniques from reducing testing to a combinational problem: ATPG for sequential devices remains a challenging field. Random and deterministic structure-oriented techniques are the state-of-the-art, but there is a growing interest in methods where the function implemented by the circuit is known. This paper shows how a test pattern may be generated while trying to disprove the equivalence of a good and a faulty machine. The algorithms are derived from Graph Theory and Model Checking. An example is analyzed to discuss the applicability and the cost of such an approach
Date: 1991
Status: Published
Language of publication: English
Uncontrolled Keywords:
Departments (original): UNSPECIFIED
Departments: DAUIN - Department of Control and Computer Engineering
DET - Department of Electronics and Telecommunications
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    Date Deposited: 13 Oct 2010 18:56
    Last modification data (IRIS): 25 Nov 2013 11:53:15
    Update date (PORTO): 28 Oct 2014 12:58
    Id Number (DOI): 10.1007/BFb0023722
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