A methodology for system-level design for verifiability

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Item Type: Proceeding
MIUR type: Proceedings > Proceedings
Title: A methodology for system-level design for verifiability
Authors string: Camurati P., Corno F., Prinetto P.
University authors:
Page Range: pp. 80-91
Referee type: Not specified type
Publisher: Springer
ISBN: 354056778X
ISSN: 0302-9743
Volume: 683
Event Title: IFIPWG10.2 Advanced Research Working Conference, CHARME'93
Event Location: Arles (FRA)
Event Dates: May 24–26, 1993
Abstract: Working at system level is attracting increasing interest. New issues must be taken into account, such as validation and verification at all steps. This paper presents a system-level design methodology that supports verification. Starting from a description in a proper subset of VHDL, a Petri Net description is obtained and used for validation purposes and for building the corresponding automaton. An efficient BDD-based tool for Process Algebra manipulation supports formal equivalence proofs. Experimental results show that the approach is feasible also for real-size industrial cases
Date: 1993
Status: Published
Language of publication: English
Uncontrolled Keywords:
Departments (original): UNSPECIFIED
Departments: DAUIN - Department of Control and Computer Engineering
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    Date Deposited: 13 Oct 2010 23:17
    Last modification data (IRIS): 21 Jan 2013 13:18:39
    Update date (PORTO): 28 Oct 2014 12:57
    Id Number (DOI): 10.1007/BFb0021716
    Permalink: http://porto.polito.it/id/eprint/2374692
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