Speeding-up Fault Injection Campaigns in VHDL models

Item Type: Proceeding
MIUR type: Proceedings > Proceedings
Title: Speeding-up Fault Injection Campaigns in VHDL models
Authors string: B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante
University authors:
Page Range: pp. 27-36
Referee type: Not specified type
Publisher: Springer
ISBN: 3540411860
ISSN: 0302-9743
Volume: 1943
Event Title: Computer Safety, Reliability and Security 19th International Conference, SAFECOMP 2000
Event Location: Rotterdam (NLD)
Event Dates: October 24–27, 2000
Abstract: Simulation-based Fault Injection in VHDL descriptions is increasingly common due to the popularity of top-down design flows exploiting this language. This paper presents some techniques for reducing the time to perform the required simulation experiments. Static and dynamic methods are proposed to analyze the list of faults to be injected, removing faults as soon as their behavior is known. Common features available in most VHDL simulation environments are also exploited. Experimental results show that the proposed techniques are able to reduce the time required by a typical Fault Injection campaign by a factor ranging from 43.9% to 96.6%
Date: 2000
Status: Published
Language of publication: English
Uncontrolled Keywords:
Departments (original): DAUIN - Control and Computer Engineering
Departments: DAUIN - Department of Control and Computer Engineering
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    Date Deposited: 14 Oct 2010 14:33
    Last modification data (IRIS): 25 Nov 2013 11:01:19
    Update date (PORTO): 28 Oct 2014 12:59
    Id Number (DOI): 10.1007/3-540-40891-6_3
    Permalink: http://porto.polito.it/id/eprint/2374722
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