On-chip Thermal Modeling Based on SPICE Simulation

Item Type: Proceeding
MIUR type: Proceedings > Proceedings
Title: On-chip Thermal Modeling Based on SPICE Simulation
Authors string: Wei L.; Calimera A.; Nannarelli A.; Macii E.; Poncino M.
University authors:
Page Range: pp. 66-75
Publisher: Springer
ISBN: 9783642118012
ISSN: 0302-9743
Volume: 5953
Event Title: 19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009
Event Location: Delft (NL)
Event Dates: September 9-11, 2009
Abstract: With technology scaled to deep submicron regime, temperature and temperature gradient have emerged as important design criteria. Elevated temperatures, spatial and temporal temperature variations and on-chip hotspot not only affect timing in both transistors and interconnects but also degrade circuit reliability. A SPICE simulation based thermal modeling method is proposed in this paper. Experiments on a set of tests show the correlations between functional and spatial hotspots in a circuit implemented in STM 65nm technologies
Date: 2010
Status: Published
Language of publication: English
Uncontrolled Keywords:
Departments (original): DAUIN - Control and Computer Engineering
Departments: DAUIN - Department of Control and Computer Engineering
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    Subjects: Area 09 - Ingegneria industriale e dell'informazione > SISTEMI DI ELABORAZIONE DELLE INFORMAZIONI
    Date Deposited: 22 Dec 2010 12:46
    Last modification data (IRIS): 08 Feb 2016 09:19:13
    Update date (PORTO): 10 Feb 2016 03:44
    Id Number (DOI): 10.1007/978-3-642-11802-9_11
    Permalink: http://porto.polito.it/id/eprint/2380165
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