This paper analyzes the generation and the propagation in system-on-chips of the switching noise due to embedded core logic blocks. Such disturbances contribute to degrade the performance of the other on-chip circuits and cause unwanted electromagnetic emission. These parasitic effects can be largely ascribed to the steep currents that flow into the power supply interconnects of the core logic blocks and to the parasitic coupling of the system-on-chip building blocks through the silicon substrate they share. In this work it is shown that the substrate voltage bounce due to the switching noise can be significantly attenuated if conventional low-impedance DC power supplies are replaced by high-impedance one. The effectiveness of the proposed approach is validated through computer simulations and experimental tests carried out on the digital core block of a test chip.

On the use of High-Impedance Power Supplies to Reduce the Substrate Switching Noise in System-on-Chips / Fiori, Franco. - In: MICROELECTRONICS RELIABILITY. - ISSN 0026-2714. - STAMPA. - 52:1(2012), pp. 282-288. [10.1016/j.microrel.2011.09.016]

On the use of High-Impedance Power Supplies to Reduce the Substrate Switching Noise in System-on-Chips

FIORI, Franco
2012

Abstract

This paper analyzes the generation and the propagation in system-on-chips of the switching noise due to embedded core logic blocks. Such disturbances contribute to degrade the performance of the other on-chip circuits and cause unwanted electromagnetic emission. These parasitic effects can be largely ascribed to the steep currents that flow into the power supply interconnects of the core logic blocks and to the parasitic coupling of the system-on-chip building blocks through the silicon substrate they share. In this work it is shown that the substrate voltage bounce due to the switching noise can be significantly attenuated if conventional low-impedance DC power supplies are replaced by high-impedance one. The effectiveness of the proposed approach is validated through computer simulations and experimental tests carried out on the digital core block of a test chip.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2440591
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