An on-chip all-digital PV-monitoring architecture for digital IPs

Item Type: Proceeding
MIUR type: Proceedings > Proceedings
Title: An on-chip all-digital PV-monitoring architecture for digital IPs
Authors string: H. Karimiyan;A. Calimera;A. Macii;E. Macii;M. Poncino
University authors:
Page Range: pp. 162-172
Publisher: Springer
ISSN: 0302-9743
Volume: 6951
Event Title: 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011
Event Location: Madrid (SP)
Event Dates: September 26-29, 2011
Abstract: This paper presents an on-chip all-digital sensor architecture to capture process variation information. The proposed solution is based on the concept of variation amplification and uses the propagation delay measurement in a chain composed of series connected pass-transistors. The proposed sensor circuit is able to capture the local variation of nMOS and pMOS transistor individually. A sensor block is proposed, which contains N-type and P-type sensor circuit along with scan, control, and measurement circuitry. An array of sensor blocks with scan chain connection gathers process variation information all across the die. Detailed SPICE level simulations conducted for an industrial 45nm CMOS technology indicates its feasibility in sensing, and on-chip all-digital measurement of process variation effect
Date: 2011
Status: Published
Language of publication:
Uncontrolled Keywords:
Departments (original): DAUIN - Control and Computer Engineering
Departments: DAUIN - Department of Control and Computer Engineering
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    Subjects: Area 09 - Ingegneria industriale e dell'informazione > SISTEMI DI ELABORAZIONE DELLE INFORMAZIONI
    Date Deposited: 31 Dec 2011 15:30
    Last modification data (IRIS): 13 Apr 2016 14:09:01
    Update date (PORTO): 15 Apr 2016 03:44
    Id Number (DOI): 10.1007/978-3-642-24154-3_17
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