Sub-row sleep transistor insertion for concurrent clock-gating and power-gating

Item Type: Proceeding
MIUR type: Proceedings > Proceedings
Title: Sub-row sleep transistor insertion for concurrent clock-gating and power-gating
Authors string: K. Lingasubramanian, A. Calimera, A. Macii, E. Macii, M. Poncino
University authors:
Page Range: pp. 214-225
Journal or Publication Title: LECTURE NOTES IN COMPUTER SCIENCE
Publisher: Springer
ISBN: 9783642241536
ISSN: 0302-9743
Volume: 6951
Event Title: 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011
Event Location: Madrid (SP)
Event Dates: September 26-29, 2011
Abstract: Concurrent clock gating (CG) and power gating (PG) can help to tackle both static and dynamic power simultaneously, thereby enabling the design of low-power and energy efficient applications. Unfortunately the automatic integration of the two techniques in standard design flows is limited by several technical impediments. Among them, physical constraints during the Sleep Transistor Insertion (STI) imposed by row-based layout rules are certainly the most critical. Although determining the feasibility of the whole clock-gating and power-gating (CG-PG) integration, the adopted STI methodology may have drastic effects on several circuit metrics, like operating frequency, throughput and power savings. In this paper we introduce a layout-friendly STI approach for fine-grained CG-PG inclusion. The proposed method, that is aware of the timing-driven strategies adopted by most of the commercial placer tools, allows sub-row insertion of independent sleep-transistor cells, therefore enabling finer resolution in the CG-PG integration, along with minimal cell displacement and negligible layout disruption. This enables a larger number of cells to be power-gated (i.e., larger potential power-savings w.r.t. state-of-the-art fine-grained STI strategies), without delay overhead. Experimental results, conducted on a set of circuit benchmarks mapped onto an industrial 65nm technology, indicate that more than 50% of the total number of cells can be clock- and power-gated simultaneously, without any speed degradation
Date: 2011
Status: Published
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Departments (original): DAUIN - Control and Computer Engineering
Departments: DAUIN - Department of Control and Computer Engineering
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    Subjects: Area 09 - Ingegneria industriale e dell'informazione > SISTEMI DI ELABORAZIONE DELLE INFORMAZIONI
    Date Deposited: 31 Dec 2011 15:12
    Last Modified: 10 Jul 2014 00:02
    Id Number (DOI): 10.1007/978-3-642-24154-3_22
    Permalink: http://porto.polito.it/id/eprint/2471390
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