H.264/AVC is currently the most commonly utilized video coding format because of its high coding efficiency compared to its predecessors. Video coding is achieved by exploiting temporal and spatial redundancies and Motion Estimation (ME) is one of the main tools employed for eliminating temporal redundancies. It is the most critical and time consuming tool in the whole encoder and typically requires 60-80% of the total computational time during the encoding process. One of the major work in this thesis is focused on implementation of low complexity block matching fast search motion estimation accelerators on different platforms, i.e. FPGA/ASIC and on GPU, done by our collaborative group. Similarly, the ASIC implemen- tation for motion estimation of Multi-View Coding (MVC) extension of H.264 is also the part of thesis. HEVC, the brand-new video coding standard addresses high efficient video coding. One of the tools employed to improve coding efficiency is the Discrete-Time Cosine Transform (DCT) with different transform sizes. In video compression, the DCT is widely used because it compacts the image energy at the low frequencies, making easy to discard the high frequency components. The second major part of the thesis is focused on the hardware implementation of the N-point, multiplierless DCT architecture for HEVC standard.
Low Complexity, High Quality Digital Architectures for H.264/AVC and HEVC Applications / Ahmed, Ashfaq. - (2014).
Low Complexity, High Quality Digital Architectures for H.264/AVC and HEVC Applications
AHMED, ASHFAQ
2014
Abstract
H.264/AVC is currently the most commonly utilized video coding format because of its high coding efficiency compared to its predecessors. Video coding is achieved by exploiting temporal and spatial redundancies and Motion Estimation (ME) is one of the main tools employed for eliminating temporal redundancies. It is the most critical and time consuming tool in the whole encoder and typically requires 60-80% of the total computational time during the encoding process. One of the major work in this thesis is focused on implementation of low complexity block matching fast search motion estimation accelerators on different platforms, i.e. FPGA/ASIC and on GPU, done by our collaborative group. Similarly, the ASIC implemen- tation for motion estimation of Multi-View Coding (MVC) extension of H.264 is also the part of thesis. HEVC, the brand-new video coding standard addresses high efficient video coding. One of the tools employed to improve coding efficiency is the Discrete-Time Cosine Transform (DCT) with different transform sizes. In video compression, the DCT is widely used because it compacts the image energy at the low frequencies, making easy to discard the high frequency components. The second major part of the thesis is focused on the hardware implementation of the N-point, multiplierless DCT architecture for HEVC standard.Pubblicazioni consigliate
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https://hdl.handle.net/11583/2532093
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