Design and characterization of a 13 bit serial-to-parallel converter in GaAs technology for smart antennas are presented. The circuit has been realized with NOR-based super-buffered enhancement/depletion logic, and optimized for a compact layout. The serial-to-parallel converter operates properly well above the 20 kHz design clock frequency.

13-bit GaAs serial-to-parallel converter with compact layout for core-chip applications / Pirola, Marco; Quaglia, Roberto; Ghione, Giovanni; Walter, Ciccognani; Ernesto, Limiti. - In: MICROELECTRONICS JOURNAL. - ISSN 0959-8324. - STAMPA. - 45:7(2014), pp. 864-869. [10.1016/j.mejo.2014.04.036]

13-bit GaAs serial-to-parallel converter with compact layout for core-chip applications

PIROLA, Marco;QUAGLIA, ROBERTO;GHIONE, GIOVANNI;
2014

Abstract

Design and characterization of a 13 bit serial-to-parallel converter in GaAs technology for smart antennas are presented. The circuit has been realized with NOR-based super-buffered enhancement/depletion logic, and optimized for a compact layout. The serial-to-parallel converter operates properly well above the 20 kHz design clock frequency.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2545737
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