In recent years, the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Under today aggressive technology scaling requirements, the STT- MRAM is affected by process variability and aging phenomena, making reliability prediction a growing concern. In this paper, we provide a methodology for predicting the reliability of an STT-MRAM based memory (assuming high thermal stability). The reliability estimation is performed at block level for different block sizes and access rates. The proposed methodology also allows for an exploration of required error correction capabilities as function of code word size to achieve desired reliability target for the memory under study.

Reliability Estimation at Block-Level Granularity of Spin-Transfer-Torque MRAMs / Vatajelu, E. I.; Indaco, M.; DI CARLO, Stefano; Prinetto, Paolo Ernesto; Rodriguez Montañés, R.; Figueras, J.. - ELETTRONICO. - (2014), pp. 75-80. (Intervento presentato al convegno 27th IEEE Defect and Fault Tolerance in VLSI and Nanotechnology Systems Symposium (DFTS) tenutosi a Amsterdam, NL nel 1-3 Oct. 2014) [10.1109/DFT.2014.6962093].

Reliability Estimation at Block-Level Granularity of Spin-Transfer-Torque MRAMs

DI CARLO, STEFANO;PRINETTO, Paolo Ernesto;
2014

Abstract

In recent years, the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Under today aggressive technology scaling requirements, the STT- MRAM is affected by process variability and aging phenomena, making reliability prediction a growing concern. In this paper, we provide a methodology for predicting the reliability of an STT-MRAM based memory (assuming high thermal stability). The reliability estimation is performed at block level for different block sizes and access rates. The proposed methodology also allows for an exploration of required error correction capabilities as function of code word size to achieve desired reliability target for the memory under study.
2014
978-1-4799-6155-9
978-1-4799-6154-2
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2571948
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