Due to increasingly stringent low-cost and small form-factor design constraints, Signal and Power Integrity analyses (SI&PI) have gained a paramount importance in the definition and optimization of mobile platforms. Operating margins are dramatically reduced in order to meet all the required design targets and constraints (extensive re-use, time-to-market, etc.). In this scenario, transistor-level simulations for platform-level analyses are inefficient and often, impractical. I/O-buffer models become essential and their accuracy is crucial for the reliability of SI&PI studies. As data-rates increase, signaling swing reduces and power-supply voltage noise becomes inevitable, state-of-the-art legacy models are limited for SI&PI co-simulations. This work summarizes the recent enhancements of “Mpilog”-class macromodels for high-speed I/O-buffers. Mpilog macromodels reproduce voltage and currents at I/O and (multiple) supply ports as weighted combinations of pull-up/pull-down static and dynamic components. The static parts are extracted via nested DC sweeps simulations and reproduced by tensor representations obtained via high-order singular value decomposition (SVD) processes. The dynamic components are described by linear state-space models identified from device's transient responses to suitable stimuli. For transmitters, the weighting functions match the output-port transitions and the dynamic supply-current profiles, capturing also the dependency of switching delays upon supply-voltage fluctuations; this is a key feature that enables Mpilog macromodels to precisely reproduce simultaneous-switching-noise (SSN) effects in complex system-level SI&PI simulations. The macromodels can be readily synthesized as SPICE netlists (including resistors, capacitors and controlled-sources) or Verilog-A codes; this allows their use in any SPICE-type electrical solver. Several examples of realistic SI&PI simulations for single-ended and differential interfaces are presented. Transistor-level simulations are compared with the corresponding ones based on Mpilog-macromodels: the resulting accuracy and the speed-up factors are extensively discussed. Comparisons with state-of-the-art legacy models (IBIS) are also discussed.

Enhanced Mpilog macromodels for Signal and Power Integrity Simulations / Signorini, Gianni; Siviero, Claudio; Stievano, IGOR SIMONE; GRIVET TALOCIA, Stefano. - ELETTRONICO. - 2015:(2015), pp. 000306-000311. (Intervento presentato al convegno International Symposium on Microelectronics tenutosi a Orlando, FL, USA nel Oct. 26-29, 2015) [10.4071/isom-2015-WA61].

Enhanced Mpilog macromodels for Signal and Power Integrity Simulations

SIGNORINI, GIANNI;SIVIERO, CLAUDIO;STIEVANO, IGOR SIMONE;GRIVET TALOCIA, STEFANO
2015

Abstract

Due to increasingly stringent low-cost and small form-factor design constraints, Signal and Power Integrity analyses (SI&PI) have gained a paramount importance in the definition and optimization of mobile platforms. Operating margins are dramatically reduced in order to meet all the required design targets and constraints (extensive re-use, time-to-market, etc.). In this scenario, transistor-level simulations for platform-level analyses are inefficient and often, impractical. I/O-buffer models become essential and their accuracy is crucial for the reliability of SI&PI studies. As data-rates increase, signaling swing reduces and power-supply voltage noise becomes inevitable, state-of-the-art legacy models are limited for SI&PI co-simulations. This work summarizes the recent enhancements of “Mpilog”-class macromodels for high-speed I/O-buffers. Mpilog macromodels reproduce voltage and currents at I/O and (multiple) supply ports as weighted combinations of pull-up/pull-down static and dynamic components. The static parts are extracted via nested DC sweeps simulations and reproduced by tensor representations obtained via high-order singular value decomposition (SVD) processes. The dynamic components are described by linear state-space models identified from device's transient responses to suitable stimuli. For transmitters, the weighting functions match the output-port transitions and the dynamic supply-current profiles, capturing also the dependency of switching delays upon supply-voltage fluctuations; this is a key feature that enables Mpilog macromodels to precisely reproduce simultaneous-switching-noise (SSN) effects in complex system-level SI&PI simulations. The macromodels can be readily synthesized as SPICE netlists (including resistors, capacitors and controlled-sources) or Verilog-A codes; this allows their use in any SPICE-type electrical solver. Several examples of realistic SI&PI simulations for single-ended and differential interfaces are presented. Transistor-level simulations are compared with the corresponding ones based on Mpilog-macromodels: the resulting accuracy and the speed-up factors are extensively discussed. Comparisons with state-of-the-art legacy models (IBIS) are also discussed.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2637831
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