Enhanced Mpilog macromodels for Signal and Power Integrity Simulations

Tipo di pubblicazione: Articolo in atti di convegno
Tipologia MIUR: Contributo in Atti di Convegno (Proceeding) > Contributo in atti di convegno
Titolo: Enhanced Mpilog macromodels for Signal and Power Integrity Simulations
Autori: Signorini, Gianni; Siviero, Claudio; Stievano, Igor Simone; Grivet-Talocia, Stefano
Autori di ateneo:
Intervallo pagine: 000306-000311
Tipo di referee: Esperti anonimi
Volume: 2015
Titolo del convegno: International Symposium on Microelectronics
Luogo dell'evento: Orlando, FL, USA
Data dell'evento: Oct. 26-29, 2015
Abstract: Due to increasingly stringent low-cost and small form-factor design constraints, Signal and Power Integrity analyses (SI&PI) have gained a paramount importance in the definition and optimization of mobile platforms. Operating margins are dramatically reduced in order to meet all the required design targets and constraints (extensive re-use, time-to-market, etc.). In this scenario, transistor-level simulations for platform-level analyses are inefficient and often, impractical. I/O-buffer models become essential and their accuracy is crucial for the reliability of SI&PI studies. As data-rates increase, signaling swing reduces and power-supply voltage noise becomes inevitable, state-of-the-art legacy models are limited for SI&PI co-simulations. This work summarizes the recent enhancements of "Mpilog"-class macromodels for high-speed I/O-buffers. Mpilog macromodels reproduce voltage and currents at I/O and (multiple) supply ports as weighted combinations of pull-up/pull-down static and dynamic components. The static parts are extracted via nested DC sweeps simulations and reproduced by tensor representations obtained via high-order singular value decomposition (SVD) processes. The dynamic components are described by linear state-space models identified from device's transient responses to suitable stimuli. For transmitters, the weighting functions match the output-port transitions and the dynamic supply-current profiles, capturing also the dependency of switching delays upon supply-voltage fluctuations; this is a key feature that enables Mpilog macromodels to precisely reproduce simultaneous-switching-noise (SSN) effects in complex system-level SI&PI simulations. The macromodels can be readily synthesized as SPICE netlists (including resistors, capacitors and controlled-sources) or Verilog-A codes; this allows their use in any SPICE-type electrical solver. Several examples of realistic SI&PI simulations for single-ended and differential interfaces are presented. Transistor-level simulations are compared with the corresponding ones based on Mpilog-macromodels: the resulting accuracy and the speed-up factors are extensively discussed. Comparisons with state-of-the-art legacy models (IBIS) are also discussed
Data: 2015
Status: Pubblicato
Lingua della pubblicazione: Inglese
Parole chiave: signal integrity, power integrity, macromodeling, high-speed i/os
Dipartimenti (originale): DET - Dipartimento di Elettronica e Telecomunicazioni
Dipartimenti: DET - Dipartimento di Elettronica e Telecomunicazioni
URL correlate:
Area disciplinare: Area 09 - Ingegneria industriale e dell'informazione > ELETTROTECNICA
Data di deposito: 17 Mar 2016 15:12
Data ultima modifica (IRIS): 17 Mar 2016 14:12:57
Data inserimento (PORTO): 19 Mar 2016 04:33
Numero Identificativo (DOI): 10.4071/isom-2015-WA61
Permalink: http://porto.polito.it/id/eprint/2637831
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