Design Methods and Tools for Nanocomputing: from Silicon Nanoarrays to Nano Magnetic Logic

Complementary metal-oxide semiconductor (CMOS) technology has driven the electronic scenario for the last 40 years. The exponential grow of computing power implicates technological challenges, such as scaling transistor sizes, increasing clock frequency and reducing the power consumption. These goals raise dramatically the manufacturing cost with every new technology node. The projections of the ITRS roadmap report tell us that the scaling will be also influenced by fundamental physical limits. These observations have stimulated researchers from industry and academia to investigate possible feasible alternatives to CMOS technology. Since at the time of writing is difficult to find a clear winner, many possibilities are studied. They are based on different computational variables such as charge controlled (i.e. transistors) or magnetic field controlled devices. But, all of them have three aspects in common: i) the manufacturing process is still not mature, so they have to deal with a high defect rate; ii) the high density expected from these new devices arise problems related to the design automation field; iii) currently no tools, specifically targeted for emerging devices, are available on the market that allow researchers to investigate these technologies. In fact, it is rather difficult to find a toolchain of existing software able to provide a complete design flow from nanodevice simulation to floorplanning, place and route, and nanoarchitecture simulation and evaluation, able to handle emerging devices related constraints. This manuscript focuses on the development of a CAD tool for nanotechnologies, named ToPoliNano. It has the ability, starting from the VHDL description of the circuit, to automatically generate the physical layout choosing a target nanotechnology. At the time of writing two technologies are supported: silicon nanorrays and in-plane NanoMagnetic Logic. After the layout phase, the user can simulate the circuit behavior with an integrated simulation engine. In this work, three beyond CMOS technologies are investigated and analyzed from an architectural point of view. The first one is based on silicon nanoarrays, the last two come from the Quantum dot Cellular Automata (QCA) family, the in-plane Nano Magnetic Logic (iNML) and the perpendicular Nano Magnetic Logic (pNML). The aim of this thesis is to analyze the layout constrains of these emerging technologies making an architectural exploration. The investigation and the benchmarking is enabled thanks to ToPoliNano, which has been enriched, during my PhD, of a place and route engine and a fault injection mechanism to verify circuits robustness. These features implementation will be discussed more in detail respectively in part 2 and 1. After a brief technological background provided in the introduction, the thesis is divided in three main parts dedicated to the three technologies analyzed: silicon nanoarray, iNML and pNML. In part 1 the high defect rate of silicon nanoarray technology is discussed and analyzed in order to find a method to design more reliable circuits. A new methodology has been developed and tested through our CAD tool ToPoliNano. Fault tolerant circuits have been tested injecting different fault maps and evaluating the output error rate and yield. In part 2, the main working structure of the layout engine and the layout constraints of iNML technology are introduced. In part 2, first the main working principle and the layout constrains are presented to the reader. Then, a detailed description of the design flow implemented in ToPoliNano will be presented. The place and route engine implemented in ToPoliNano will be analyzed and described in detail with examples. The algorithms are compared and results are provided in the last part of this section. In the last part, the pNML technology will be analyzed. In particular, this work has been done in collaboration with the Lehrstuhl für Technische Elektronik (LTE) institute at the Technical University of Munich (TUM). Here, after a brief introduction about the up to date fabrication process, some experimental data are presented in order to extract useful information for developing a drawing tool. The idea is to design a drawing tool that enables the final user to design 3D pNML based circuits. The tool should embed data collected from experiments and it should able to automatically export the VHDL file that described the drawn architecture. In this way, the behavior and the correctness of the circuit can be verified using Modelsim simulator from Mentor Graphics. However, this part of the thesis in currently under development. Thus, only an overview of the whole flow will be provided.