The key characteristics of the next generation of ICs for wearable applications include high integration density, small area, low power consumption, high energy-efficiency, reliability and enhanced mechanical properties like stretchability and transparency. The proper mix of new materials and novel integration strategies is the enabling factor to achieve those design specifications. Moving toward this goal, we introduce a graphene-based regular logic-array structure for energy efficient digital computing. It consists of graphene p-n junctions arranged into a regular mesh. The obtained structure resembles that of Programmable Logic Arrays (PLAs), hence the name Graphene-PLAs (GPLAs); the high expressive power of graphene p-n junctions and their resistive nature enables the implementation of ultra-low power adiabatic logic circuits.

Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture / Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - ELETTRONICO. - (2016), pp. 145-150. (Intervento presentato al convegno 26th ACM Great Lakes Symposium on VLSI, GLSVLSI 2016 tenutosi a usa nel 2016) [10.1145/2902961.2902970].

Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture

TENACE, VALERIO;CALIMERA, ANDREA;MACII, Enrico;PONCINO, MASSIMO
2016

Abstract

The key characteristics of the next generation of ICs for wearable applications include high integration density, small area, low power consumption, high energy-efficiency, reliability and enhanced mechanical properties like stretchability and transparency. The proper mix of new materials and novel integration strategies is the enabling factor to achieve those design specifications. Moving toward this goal, we introduce a graphene-based regular logic-array structure for energy efficient digital computing. It consists of graphene p-n junctions arranged into a regular mesh. The obtained structure resembles that of Programmable Logic Arrays (PLAs), hence the name Graphene-PLAs (GPLAs); the high expressive power of graphene p-n junctions and their resistive nature enables the implementation of ultra-low power adiabatic logic circuits.
2016
9781450342742
9781450342742
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2654866