FPGA-based digital predistortion of a 3.5 GHz GaN Doherty power amplifier

In this paper, a baseband predistortion scheme is applied and implemented into real-time FPGA to linearize a Doherty power amplifier for wireless applications. The baseband behavioral models of the Doherty amplifier are based on the Memory Polynomial approach and the direct learning method is applied to estimate the model of the predistorter. For our Doherty power amplifier with a 256- QAM I/Q input signal with 7.4 dB Peak to Average Power Ratio at a center frequency of 3.5 GHz, a significant improvement of nearly 10 dB Adjacent Channel Power Ratio reduction has been obtained with a 36.8 dBm average output power and a 45% average efficiency.