This brief describes a novel integration strategy that aims at bringing adiabatic computation to large scale integration. The proposed design solution, built upon logic primitives packed into regular arrays, the quasi-adiabatic-logic-arrays (QALAs), is well suited not just for today's silicon transistors but also for emerging devices. QALAs are indeed a viable path toward the integration of ultra-low power ICs using devices with a gapless energy spectrum, graphene p-n junctions in particular. The design of QALA circuits is supported by a dedicated RTL-to-device design framework whose kernel consists of a new area/delay-driven logic synthesis and optimization engine. Simulation results conducted on several benchmarks mapped both onto silicon (using 40 nm MOSFETs) and graphene (using electrostatically controlled p-n junctions) show the proposed methodology provides adiabatic logic circuits with a power-delay-product that is one order of magnitude smaller than that of state-of-the-art adiabatic circuits implemented using pass-transistor logic and conventional logic synthesis flows

Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs / Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747. - STAMPA. - 63:12(2016), pp. 1111-1115. [10.1109/TCSII.2016.2624145]

Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs

TENACE, VALERIO;CALIMERA, ANDREA;MACII, Enrico;PONCINO, MASSIMO
2016

Abstract

This brief describes a novel integration strategy that aims at bringing adiabatic computation to large scale integration. The proposed design solution, built upon logic primitives packed into regular arrays, the quasi-adiabatic-logic-arrays (QALAs), is well suited not just for today's silicon transistors but also for emerging devices. QALAs are indeed a viable path toward the integration of ultra-low power ICs using devices with a gapless energy spectrum, graphene p-n junctions in particular. The design of QALA circuits is supported by a dedicated RTL-to-device design framework whose kernel consists of a new area/delay-driven logic synthesis and optimization engine. Simulation results conducted on several benchmarks mapped both onto silicon (using 40 nm MOSFETs) and graphene (using electrostatically controlled p-n junctions) show the proposed methodology provides adiabatic logic circuits with a power-delay-product that is one order of magnitude smaller than that of state-of-the-art adiabatic circuits implemented using pass-transistor logic and conventional logic synthesis flows
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2655265