A reconfigurable array architecture for NML

NanoMagnet Logic (NML) is one of the most promising emerging technologies, in particular for its low power consumption and for the capability to mix logic and memory in the same device. At the same time this technology has some drawbacks, the most important of which is the long delay of wires and the correlation between layout and circuit timing. From a technological point of view, MagnetoElastic NML (ME-NML) is one of the proposed improvements that could address some of these drawbacks. From an architectural point of view, instead, to exploit the peculiar characteristics of NML and reduce the impact of its drawbacks, parallel solutions like Systolic Arrays can be adopted. Systolic Arrays are commonly used as hardware accelerators dedicated to a single algorithm, and for this reason their field of use has been extremely limited. Reconfigurable Arrays can overcome this limitation. In this article we first introduce our Reconfigurable Systolic Array. It can be configured to execute different algorithms and it is therefore an ideal architecture for NML. The Reconfigurable Systolic Array has been first designed at a RTL level in CMOS and synthesized using a 28nm technology. Then, it has been synthesized and simulated in classic NML using ToPoliNano, the first existing tool for NML. Finally, a custom layout based on ME-NML has been designed and we have estimated area and power dissipation. Comparison among the technologies show that ME-NML is extremely promising in terms of area occupation and power dissipation. Even if the technology is not yet mature it can already compete with CMOS.