Signal and Power Integrity (SI/PI) analyses assume a paramount importance to ensure a secure integration of high-speed communication interfaces in low-cost highly-integrated System-in-Package(s) (SiP) for mobile applications. In an iterative fashion, design and time-domain SI/PI verifications are alternated to assess and optimize system functionality. The resulting complexity of the analysis limits simulation coverage and requires extremely long runtimes (hours, days). In order to ensure post-silicon correlation, electrical macromodels of Package/PCB parasitics and high-speed I/Os can be generated and included in the testbenches to expedite simulations. Using as example an LP-DDR2 memory interface to support the operations of a mobile digital base-band processor, we have developed and applied a macromodelling flow to demonstrate simulation run-time speed-up factors (x1200+), and enable interface-level analyses to study the effects of Package/PCB parasitics on signals and PDNs, as well as the corresponding degradation in the timing budget.

Macromodel-based Signal and Power Integrity simulations of an LP-DDR2 interface in mSiP / G., Signorini; GRIVET TALOCIA, Stefano; Stievano, IGOR SIMONE; L., Fanucci. - STAMPA. - (2014), pp. 1-4. (Intervento presentato al convegno 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) tenutosi a Grenoble, F nel Jun. 30, 2014 - Jul. 3, 2014) [10.1109/PRIME.2014.6872719].

Macromodel-based Signal and Power Integrity simulations of an LP-DDR2 interface in mSiP

GRIVET TALOCIA, STEFANO;STIEVANO, IGOR SIMONE;
2014

Abstract

Signal and Power Integrity (SI/PI) analyses assume a paramount importance to ensure a secure integration of high-speed communication interfaces in low-cost highly-integrated System-in-Package(s) (SiP) for mobile applications. In an iterative fashion, design and time-domain SI/PI verifications are alternated to assess and optimize system functionality. The resulting complexity of the analysis limits simulation coverage and requires extremely long runtimes (hours, days). In order to ensure post-silicon correlation, electrical macromodels of Package/PCB parasitics and high-speed I/Os can be generated and included in the testbenches to expedite simulations. Using as example an LP-DDR2 memory interface to support the operations of a mobile digital base-band processor, we have developed and applied a macromodelling flow to demonstrate simulation run-time speed-up factors (x1200+), and enable interface-level analyses to study the effects of Package/PCB parasitics on signals and PDNs, as well as the corresponding degradation in the timing budget.
2014
9781479949946
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2560336
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