Pubblicazioni dell'autore: Valerio Tenace [Rubrica]

Livello precedente
Esporta come [feed] Atom [feed] DataCiteXML [feed] RSS 1.0 [feed] RSS 2.0
Vai a: 2017 | 2016 | 2015 | 2014 | 2012
Numero di pubblicazioni : 14.

2017

Capitolo di libro Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2017)
Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits. In: VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability. Springer, pp. 60-82. ISBN 978-3-319-67103-1

2016

Tesi di dottorato Valerio, Tenace (2016)
CAD Tools for Graphene-Based Electronic Circuits. Tesi di dottorato [Disponibilità ristretta]
[img]

Articolo in atti di convegno Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2016)
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies. In: 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montreal's Sheraton Centre, can, 2016. p. 2897
Web of Science: 0 - Scopus: 0

Articolo in atti di convegno Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2016)
Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture. In: 26th ACM Great Lakes Symposium on VLSI, GLSVLSI 2016, usa, 2016. pp. 145-150
Web of Science: 0 - Scopus: 1

Articolo in atti di convegno Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2016)
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits. In: 24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallin, Estonia, 26-28 Settembre 2016. pp. 1-6
Web of Science: 0 - Scopus: 1

Articolo di rivista Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2016)
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs. In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747
Web of Science: 0 - Scopus: 1

2015

Articolo in atti di convegno Miryala, Sandeep; Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo; Amarú, Luca; De Micheli, Giovanni; Gaillardon, Pierre-Emmanuel (2015)
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. In: Great Lakes Symposium on VLSI. pp. 39-44 [Disponibilità ristretta]
Scopus: 3
[img]

Articolo in atti di convegno Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2015)
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits. In: 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015, usa, 2015. pp. 1-6 [Disponibilità ristretta]
Web of Science: 0 - Scopus: 8
[img]

Articolo di rivista Miryala, Sandeep; Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2015)
Ultra-low power circuits using graphene p-n junctions and adiabatic computing. In: MICROPROCESSORS AND MICROSYSTEMS, vol. 39 n. 8, pp. 962-972. - ISSN 0141-9331
Web of Science: 2 - Scopus: 3
[img]
Preview

2014

Articolo in atti di convegno Tenace V.; Calimera A.; Macii E.; Poncino M. (2014)
Pass-XNOR Logic: A new Logic Style for P-N Junction based Graphene Circuits. In: DATE-14: ACM/IEEE Design, Automation and Test in Europe.
Web of Science: 0 - Scopus: 11

Articolo in atti di convegno V. Tenace; A. Calimera; E. Macii; M. Poncino (2014)
Quantifying the figures of merit of graphene-based adiabatic Pass-XNOR Logic (PXL) circuits. In: PRIME-14: IEEE Conference on Ph.D. Research in Microelectronics and Electronics. pp. 1-4
Web of Science: 0 - Scopus: 2

Articolo di rivista Tenace V.; Miryala S.; Calimera A.; Macii A.; Macii E.; Poncino M. (2014)
Row-Based Body-Bias Assignment for Dynamic Thermal Clock-Skew Compensation. In: MICROELECTRONICS JOURNAL, vol. 45 n. 5, pp. 530-538. - ISSN 0959-8324
Web of Science: 0 - Scopus: 1

2012

Articolo in atti di convegno Tenace V.; Miryala S.; Calimera A.; Macii A.; Macii E.; Poncino M. (2012)
Layout Constrained Body-Biasing for Temperature Induced Clock-Skew Compensation. In: THERMINIC-12: IEEE International Workshop on Thermal Investigations of ICs and Systems, Budapest, September. pp. 1-6

Articolo in atti di convegno Wei L., Miryala S., Tenace V., Calimera A., Macii E., Poncino M. (2012)
NBTI effects on tree-like clock distribution networks. In: GLSVLSI-12: IEEE/ACM Great Lakes symposium on VLSI, Salt Lake City, Utah, May 2012. pp. 279-282
Scopus: 2

Questa lista è stata generata il Sat Nov 18 10:20:46 2017 CET.