Aggiornamento Repository Istituzionale e dismissione di PORTO.

Pubblicazioni dell'autore: Massimo Violante [Rubrica]

Livello precedente
Esporta come [feed] Atom [feed] DataCiteXML [feed] RSS 1.0 [feed] RSS 2.0
Vai a: In corso di stampa | 2017 | 2016 | 2015 | 2014 | 2013 | 2012 | 2011 | 2010 | 2009 | 2008 | 2007 | 2006 | 2005 | 2004 | 2003 | 2002 | 2001 | 2000 | 1999 | 1998 | 1997
Numero di pubblicazioni : 211.

In corso di stampa

Articolo di rivista Campagna S., Hussain Moazzam, Violante M.
A Light-Weight Fault Tolerance Framework for Space Computing using COTS Components. In: LECTURE NOTES IN COMPUTER SCIENCE. - ISSN 0302-9743 (In stampa)

Articolo in atti di convegno Battezzati N., Decuzzi F., Sterpone L., Violante M.
A New Software Tool for Static Analysis of SET Sensitiveness in Flash-based FPGAs. In: IEEE International Symposium on Very Large Scale of Integration (VLSI) and System-on-Chip (SoC). (In stampa)
Web of Science: 1 - Scopus: 1

2017

Articolo in atti di convegno Esposito, Stefano; Violante, Massimo (2017)
Deterministic Network On Chip for Deploying Real Time Applications on Many-core Processors. In: 2017 IEEE 23rd International Symposium on On-Line Testing and Robust Systems Design, Salonicco (GR), 3-5 Luglio 2017. pp. 21-24 [Disponibilità ristretta]
Scopus: 0
[img]

Articolo di rivista Finesso, Roberto; Marello, Omar; Misul, Daniela; Spessa, Ezio; Violante, Massimo; Yang, Yixin; Hardy, Gilles; Maier, Christian (2017)
Development and Assessment of Pressure-Based and Model-Based Techniques for the MFB50 Control of a Euro VI 3.0L Diesel Engine. In: SAE INTERNATIONAL JOURNAL OF ENGINES, vol. 10 n. 4, pp. 1538-1555. - ISSN 1946-3944
Scopus: 4

Articolo di rivista Avramenko, Serhiy; Sonza Reorda, Matteo; Violante, Massimo; Fey, Görschwin (2017)
A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms. In: JOURNAL OF ELECTRONIC TESTING, pp. 1-12. - ISSN 0923-8174 [Disponibilità ristretta]
Web of Science: 0 - Scopus: 1
[img]

Articolo di rivista Esposito, Stefano; Violante, Massimo; Sozzi, Marco; Terrone, Marco; Traversone, Massimo (2017)
A Novel Method for Online Detection of Faults Affecting Execution-Time in Multicore-Based Systems. In: ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, vol. 16 n. 4, pp. 1-19. - ISSN 1539-9087
Scopus: 1
[img]
Preview

Articolo di rivista Esposito, Stefano; Violante, Massimo (2017)
On the consolidation of mixed criticalities applications on multicore architectures. In: JOURNAL OF ELECTRONIC TESTING, pp. 1-12. - ISSN 0923-8174 [Disponibilità ristretta]
Web of Science: 0 - Scopus: 1
[img]

Articolo in atti di convegno Esposito, Stefano; Violante, Massimo (2017)
System-level architecture for mixed criticality applications on MPSoC: A space application. In: 4th IEEE International Workshop on Metrology for AeroSpace, MetroAeroSpace 2017, Padova (IT), 2017. pp. 479-483 [Disponibilità ristretta]
Scopus: 0
[img]

Articolo in atti di convegno Flenker, Tino; Malburg, Jan; Fey, Goerschwin; Avramenko, Serhiy; Violante, Massimo; Reorda, Matteo Sonza (2017)
Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects. In: 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, deu, 2017. pp. 533-538 [Disponibilità ristretta]
Scopus: 0
[img]

Articolo in atti di convegno Bagalini, Enea; Sini, Jacopo; Sonza Reorda, Matteo; Violante, Massimo; Klimesch, Herwig; Sarson, Peter (2017)
An automatic approach to perform the verification of hardware designs according to the ISO26262 functional safety standard. In: Test Symposium (LATS), 2017 18th IEEE Latin American, Bogotà, 13-15 March 2017. pp. 1-6 [Disponibilità ristretta]
Web of Science: 0 - Scopus: 0
[img]

2016

Articolo in atti di convegno Avramenko, S.; Reorda, M. Sonza; Violante, M.; Fey, G. (2016)
Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables. In: 17th IEEE Latin-American Test Symposium, LATS 2016, bra, 2016. pp. 14-19 [Disponibilità ristretta]
Web of Science: 0 - Scopus: 1
[img]

Capitolo di libro Esposito, Stefano; Violante, Massimo (2016)
Commercial Off-the-Shelf Components in Space Applications. In: Semiconductor Devices in Harsh Conditions / Kirsten Weide-Zaage, Malgorzata Chrzanowska-Jeske. CRC PRESS, pp. 3-20. ISBN 9781498743808 [Disponibilità ristretta]
[img]

Articolo in atti di convegno Bagalini, Enea; Violante, Massimo (2016)
Development of an automated test system for ECU software validation: an industrial experience. In: Biennial Baltic Electronics Conference (BEC 2016), Tallinn (Estonia), 3-5 Oct. 2016. pp. 103-106 [Disponibilità ristretta]
Web of Science: 0 - Scopus: 0
[img]

Capitolo di libro Stefano Esposito; Massimo Violante (2016)
Mitigating Soft Errors in Processors Cores Embedded in System-on Programmable-Chips. In: FPGAs and Parallel Architectures for Aerospace Applications. Springer, pp. 219-238. ISBN 9783319143521

Articolo in atti di convegno Esposito, Stefano; Avramenko, Serhiy; Violante, Massimo (2016)
On the consolidation of mixed criticalities applications on multicore architectures. In: 2016 17th Latin-American Test Symposium (LATS), Foz-do-Iguacu (Brasile), 6-8 Aprile 2016. pp. 57-62 [Disponibilità ristretta]
Web of Science: 1 - Scopus: 3
[img]

Articolo in atti di convegno Avramenko, Serhiy; Sonza Reorda, Matteo; Violante, Massimo; Fey, Görschwin; Mess,Jan-Gerd; Schmidt, Robert (2016)
On the robustness of DCT-based compression algorithms for space applications. In: IEEE International Symposium on On-Line Testing and Robust System Design, Sant Feliu de Guixols, 4 – 6 July 2016. pp. 1-2 [Disponibilità ristretta]
Web of Science: 0 - Scopus: 1
[img]

Articolo in atti di convegno Esposito, Stefano; Violante, Massimo; Sozzi, Marco; Terrone, Marco; Traversone, Massimo (2016)
Online Time Interference Detection in Mixed-Criticality Applications on Multicore Architectures using Performance Counters. In: 22nd IEEE International Symposium on On-Line Testing and Robust System Design, Sant Feliu de Guixols (Spagna), 4-6 July 2016. [Disponibilità ristretta]
Web of Science: 1 - Scopus: 3
[img]

2015

Articolo di rivista Esposito, Stefano; Albanese, Cristian; Alderighi, Monica; Casini, Fabio; Giganti, Luca; Esposti, Maria Livia; Monteleone, Claudio; Violante, Massimo (2015)
COTS-Based High-Performance Computing for Space Applications. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 62 n. 6, pp. 2687-2694. - ISSN 0018-9499 [Disponibilità ristretta]
Web of Science: 2 - Scopus: 4
[img]

Articolo di rivista Bagalini, Enea; Violante, Massimo (2015)
Designing Autonomous Race Car Models for Learning Advanced Topics in Hard Real-Time System. In: INTERNATIONAL JOURNAL OF ROBOTICS APPLICATIONS AND TECHNOLOGIES, vol. 3 n. 1, pp. 1-22. - ISSN 2166-7195 [Disponibilità ristretta]
[img]

Articolo in atti di convegno Bari F.; Mereu D.; Damarco C.; Greco C.; Malan S.; Marchetto G.; Roa Tirado S.; Tisseur R.; Violante M.; Zangari G.; Caruso S.; Masoero M.; Saba F. (2015)
The EcoThermo project: key and innovative aspects. In: 6th International Building Physics Conference, IBPC 2015, Torino, 15-17 June 2015. pp. 2977-2982
Web of Science: 4 - Scopus: 4
[img]

Articolo in atti di convegno Enea, Bagalini; Massimo, Violante; Hakob, Hakobyan (2015)
Evaluation of error effects on a biomedical system. In: IEEE East- West Design & Test Symposium, Batumi (Georgia), September 26-29, 2015. pp. 39-42 [Disponibilità ristretta]
Web of Science: 0 - Scopus: 1
[img]

Articolo in atti di convegno Avramenko, Serhiy; Esposito, Stefano; Violante, Massimo; Sozzi, Marco; Traversone, Massimo; Binello, Marco; Terrone, Marco (2015)
An Hybrid Architecture for consolidating mixed criticality applications on multicore systems. In: IEEE International On-Line Testing Symposium. pp. 26-29
Web of Science: 4 - Scopus: 6

Articolo di rivista Giordano, R.; Aloisio, A.; Bocci, V.; Capodiferro, M.; Izzo, V.; Sterpone, L.; Violante, M. (2015)
Layout and Radiation Tolerance Issues in High-Speed Links. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 62 n. 6, pp. 3177-3185. - ISSN 0018-9499
Web of Science: 1 - Scopus: 0

2014

Articolo in atti di convegno H. Hakobyan , P. Rech, M. Sonza Reorda, M. Violante (2014)
Early Reliability Evaluation of a Biomedical System. In: 2014 9th International Design & Test Symposium, Algiers, Algeria, December 2014. pp. 45-50 [Disponibilità ristretta]
Web of Science: 1
[img]

Capitolo di libro Massimo Violante;Gianpaolo Macario;Salvatore Campagna (2014)
Embedded virtualization techniques for automotive infotainment applications. In: Handbook of Research on Embedded Systems Design. IGI Global, pp. 372-387. ISBN 9781466661943
Scopus: 0

Articolo in atti di convegno Bocci, V. ; Capodiferro, M. ; Giordano, R. ; Izzo, V.; Sterpone, L.; Violante, M. (2014)
Layout and radiation tolerance issues in high-speed links for TDAQ systems. In: Real Time Conference (RT), 2014 19th IEEE-NPSS. pp. 1-2
Web of Science: 0 - Scopus: 0

2013

Articolo di rivista Prashant D. Joshi; Massimo Violante (2013)
IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems Guest Editorial. In: JOURNAL OF ELECTRONIC TESTING, vol. 29, pp. 259-260. - ISSN 0923-8174
Web of Science: 0 - Scopus: 0

Articolo di rivista Aloisio A.; Bocci V. ; Giordano R. ; Izzo V. ; Sterpone, L. ; Violante, M. (2013)
Power Consumption Versus Configuration SEUs in Xilinx Virtex-5 FPGAs. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 60 n. 5, pp. 3502-3507. - ISSN 0018-9499
Web of Science: 1 - Scopus: 1

2012

Articolo in atti di convegno Bolchini C.; Miele A.; Sandionigi C.; Ottavi M.; Pontarelli S.; Salsano A.; Metra C.; Omana M.; Rossi D.; Sonza Reorda M.; Sterpone L.; Violante M.; Gerardin S.; Bagatin M.; Paccagnella A. (2012)
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). pp. 121-125
Scopus: 4

Articolo in atti di convegno Aloisio A.; Bocci V.; Chiodi G.; Giordano R.; Izzo V.; Sterpone L.; Violante M. (2012)
SEU effects on power consumption in FPGAs. In: IEEE Real Time Conference, San Francisco, USA, June 2012. pp. 1-5
Web of Science: 0 - Scopus: 0

Articolo in atti di convegno Campagna S., Violante M. (2012)
An hybrid architecture to detect transient faults in microprocessors: An experimental validation. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012. pp. 1433-1438
Web of Science: 2 - Scopus: 6

Articolo in atti di convegno Costenaro E., Violante M. , Alexandrescu D. (2012)
A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories. In: On-Line Testing Symposium (IOLTS), 2011 IEEE 17th International. pp. 49-54
Scopus: 4

2011

Capitolo di libro Sonza Reorda M., Sterpone L., Violante M. (2011)
Advanced technologies for transient faults detection and compensation. In: Design and test technology for dependable Systems-on-Chip / R. Ubar, J. Raik, H.T. Vierhaus (ed.). IGI Global, pp. 132-154. ISBN 9781609602123

Articolo di rivista Battezzati N.; Margaglia F.; Violante M.; Decuzzi F.; Merodio Codinachs D.; Bancelin B. (2011)
Application-oriented SEU cross-section of aprocessor soft core for Atmel RHBD FPGAs. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 58 n. 3, pp. 987-992. - ISSN 0018-9499
Web of Science: 3 - Scopus: 3

Articolo di rivista Guzman-Miranda H.; Sterpone L.; Violante M.; Aguirre M.; Gutierrez-Rizo M. (2011)
Coping With the Obsolescence of Safety - or Mission-Critical Embedded Systems Using FPGAs. In: IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS n. 58, pp. 814-821. - ISSN 0278-0046
Web of Science: 16 - Scopus: 22

Capitolo di libro Violante M. (2011)
Fault-Injection Techniques for Dependability Analysis: An Overview. In: Radiation Effects in Semiconductors. CRC Press, pp. 385-404. ISBN 9781439826942

Articolo in atti di convegno J. Perez Acle; M. Sonza Reorda; M. Violante (2011)
Implementing a safe embedded computing system in SRAM-based FPGAs using IP cores: A case study based on the Altera NIOS-II soft processor. In: 2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS). pp. 1-5
Scopus: 4
[img]
Preview

Articolo di rivista Sterpone L.; Violante M.; Panariti A.; Bocquillo A.; Miller F.; Buard N.; Manuzzato A.; Gerardin S.; Paccagnella A. (2011)
Layout-Aware Multi-Cell Upsets Effects Analysis on TMR Circuits Implemented on SRAM-Based FPGAs. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 58 n. 5, pp. 2325-2332. - ISSN 0018-9499
Web of Science: 6 - Scopus: 7

Articolo di rivista Sonza Reorda M.; Violante M; Meinhardt C.; Reis R. (2011)
A Low-Cost Solution for Deploying Processor Cores in Harsh Environments. In: IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, vol. 58 n. 7, pp. 2617-2626. - ISSN 0278-0046
Web of Science: 10 - Scopus: 12

Libro Battezzati N.; Sterpone L.; Violante M. (2011)
Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications. Springer Science+Business Media, pp. 1-220. ISBN 9781441975942

Capitolo di libro M. Rebaudengo, M. Sonza Reorda, M. Violante (2011)
SOFTWARE-LEVEL SOFT-ERROR MITIGATION TECHNIQUES. In: Soft Errors in Modern Electronic Systems / M. Nicolaidis. Springer, pp. 253-285. ISBN 9781441969927

Articolo in atti di convegno Hussain M.; Din A.; Violante M.; Bona B. (2011)
An adaptively reconfigurable computing framework for intelligent robotics. In: 2011 IEEE/ASME International Conference on Advanced Intelligent Mechatronics (AIM 2011), Budapest (Hungary), 3-7 July, 2011. pp. 996-1002
Web of Science: 4 - Scopus: 4
[img]
Preview

2010

Articolo in atti di convegno Battezzati N., Margaglia F., Violante M., Decuzzi F., Merodio Codinachs D., Bancelin B. (2010)
Application-oriented SEU cross-section of a processor soft core for Atmel RHBD FPGAs. In: 11th European Conference on Radiation and Its Effects on Component and Systems.

Articolo di rivista Cabodi G; Murciano M.; Violante M (2010)
Boosting Software Fault Injection for Dependability Analysis of Real-Time Embedded Applications. In: ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, vol. 10 n. 2, 24:1-24:32. - ISSN 1539-9087 [Disponibilità ristretta]
Web of Science: 3 - Scopus: 4
[img]

Articolo in atti di convegno Campagna S, Hussain M., Violante M (2010)
Hypervisor-Based Virtual Hardware for Fault Tolerance in COTS Processors Targeting Space Applications. In: Defect and Fault Tolerance in VLSI Systems (DFT), 2010 IEEE 25th International Symposium on. pp. 44-51
Web of Science: 2 - Scopus: 7

Articolo in atti di convegno Campagna S., Violante M. (2010)
A framework to support the design of COTS-based reliable space computers for on-board data handling. In: On-Line Testing Symposium (IOLTS), 2010 IEEE 16th International. pp. 91-96
Scopus: 3

Articolo in atti di convegno Bolchini C., Miele A., Sandionigi C., Battezzati N., Sterpone L., Violante M. (2010)
An integrated flow for the design of hardened circuits on SRAM-based FPGAs. In: 15th IEEE European Test Symposium. pp. 214-219
Scopus: 7

Articolo in atti di convegno Battezzati N., Serrone D. , Violante M. (2010)
A new framework for the automatic insertion of mitigation structures in circuits netlists. In: On-Line Testing Symposium (IOLTS), 2010 IEEE 16th International. pp. 190-191
Scopus: 1

2009

Articolo in atti di convegno Battezzati N.; Decuzzi F; Violante M; Briet M (2009)
Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs. In: 15th IEEE International On-Line Testing Symposium, Sesimbra-Lisbon, Portugal, 24-26 June 2009. pp. 89-94
Web of Science: 1 - Scopus: 5

Articolo in atti di convegno Gianpaolo Macario; Torchiano M.; Massimo Violante (2009)
An In-Vehicle Infotainment Software Architecture Based on Google Android. In: IEEE Symposium on Industrial Embedded Systems (SIES) 2009, Lausanne, Switzerland, July 8-10. pp. 257-260
Web of Science: 17 - Scopus: 28

Articolo in atti di convegno Sterpone L.; Violante M.; Bocquillon A.; Miller F.; Buard N.; Manuzzato A.; Gerardin S.; Pacagnella A. (2009)
Layout-aware multi-cell upsets effects analysis on TMR circuits implemented on SRAM-based FPGAs. In: Radiation and Its Effects on Components and Systems (RADECS), 2009 European Conference on.
Scopus: 0

Articolo di rivista Battezzati N.; S. Gerardin; A. Manuzzato; D. Merodio; A. Paccagnella; C. Poivey; L. Sterpone; M. Violante (2009)
Methodologies to study frequency-dependent Single Event Effects sensitivity in Flash-based FPGAs. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 56, pp. 3534-3541. - ISSN 0018-9499
Web of Science: 6 - Scopus: 9

Articolo di rivista Abate F.; L. Sterpone; C.A. Lisboa; L. Carro; M. Violante (2009)
New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 56, pp. 1992-2000. - ISSN 0018-9499
Web of Science: 10 - Scopus: 19

Articolo in atti di convegno Matteo Sonza Reorda; Massimo Violante; Cristina Meinhardt (2009)
An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs. In: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2009 (DFT09), Chicago (USA), October 2009. pp. 254-262
Web of Science: 1 - Scopus: 1

Articolo in atti di convegno Meinhardt C; Reis R; Violante M; Sonza Reorda M. (2009)
Recovery scheme for hardening system on programmable chips. In: 10th IEEE Latin American Test Workshop (LATW '09), Buzios (Brazil), 2-5 March 2009. pp. 1-6
Web of Science: 0 - Scopus: 0

Articolo in atti di convegno N. Battezzati; F. Decuzzi; Sterpone L.; M. Violante (2009)
Soft Errors in Flash-based FPGAs: Analysis Methodologies and First Results. In: Field Programmable Logic and Applications, August 31 - September 2, 2009. pp. 723-724
Web of Science: 3 - Scopus: 3

Articolo in atti di convegno Sonza Reorda M.; M. Violante; C. Meinhardt; R. Reis (2009)
A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips. In: Design, Automation & Test in Europe Conference & Exhibition (DATE '09), Nice, France, April 2009. pp. 352-357

Articolo in atti di convegno Violante M.; Esposti M.L. (2009)
A low-cost solution for developing reliable Linux-based space computers for on-board data handling. In: On-Line Testing Symposium, 2009. IOLTS 2009. 15th IEEE International.
Web of Science: 1 - Scopus: 1

Articolo in atti di convegno Abate F.; Lima Kastensmidt F; Sterpone L; Violante M (2009)
A study of the Single Event Effects Impact on Functional Mapping within Flash-based FPGAs. In: Design, Automation and Test in Europe, 20-24 April 2009.
Web of Science: 2 - Scopus: 5

2008

Articolo in atti di convegno Abate F.; Violante M (2008)
Coping with Obsolescence of Processor Cores in Critical Applications. In: IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 1-3 Oct. 2008.
Web of Science: 2 - Scopus: 2

Articolo di rivista A. Manuzzato; S. Gerardin; A. Paccagnella; Sterpone L.; M. Violante (2008)
Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumulation in commercial SRAM-based FPGAs. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 55, pp. 1968-1973. - ISSN 0018-9499
Web of Science: 11 - Scopus: 17

Articolo in atti di convegno Abate F.; Sterpone L; Violante M (2008)
Experimental Validation of Lockstep, Checkpoint, and Rollback Recovery to Detect and Correct Soft Errors in System-On-Programmable-Chips. In: Radiation Effects on Components and Systems, 10-12 September.

Articolo di rivista Eduardo Luis Rhod; Carlos Arthur Lang Lisbôa; Luigi Carro; Sonza Reorda M.; Massimo Violante (2008)
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs. In: JOURNAL OF ELECTRONIC TESTING, pp. 45-56. - ISSN 0923-8174
Web of Science: 13 - Scopus: 20

Articolo di rivista N. Battezzati; Sterpone L.; M. Violante (2008)
Monte Carlo Analysis of the Effects of Soft Errors Accumulation in SRAM-based FPGAs. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 55, pp. 3381-3387. - ISSN 0018-9499
Web of Science: 3 - Scopus: 3

Articolo di rivista F. Abate; Sterpone L.; M. Violante (2008)
A New Mitigation Approach For Soft Errors In Embedded Processors. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 55, pp. 2063-2069. - ISSN 0018-9499
Web of Science: 9 - Scopus: 9

Articolo in atti di convegno A. Manuzzato; S. Gerardin; A. Paccagnella; Sterpone L.; M. Violante (2008)
On the Static Cross Section of SRAM-Based FPGAs. In: IEEE Radiation Effects Data Workshop, 14 - 18 July 2008. pp. 94-97
Web of Science: 7 - Scopus: 9

Articolo in atti di convegno Battezzati N; Gerardin S; Manuzzato A; Paccagnella A; Rezgui S; Sterpone L.; Violante M (2008)
On the evaluation of radiation-induced transient faults in Flash-based FPGAs. In: 14th IEEE International On-Line Testing Symposium. pp. 135-140
Web of Science: 3 - Scopus: 14

Articolo in atti di convegno Alderighi M.; Casini F.; D'Angelo S.; Mancini M.; Merodio Codinachs D.; Pastore S.; Sorrenti G.; Sterpone L.; Weigand R.; Violante M. (2008)
Robustness analysis of soft error accumulation in SRAM-FPGAs using FLIPPER and STAR/RoRA. In: Radiation and Its Effects on Components and Systems (RADECS), 2008 European Conference on.
Scopus: 7

Articolo di rivista Alderighi M; Casini F; D'Angelo S; Mancini M; Pastore S; Sterpone L.; Violante M (2008)
Soft Errors in SRAM-FPGAs: a Comparison of Two Complementary Approaches. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 55, pp. 2267-2273. - ISSN 0018-9499
Web of Science: 6 - Scopus: 11

Articolo di rivista C. Bolchini; A. Miele; M. Rebaudengo; F. Salice; Sterpone L.; M. Violante (2008)
Software and Hardware Techniques for SEU Detection in IP Processors. In: JOURNAL OF ELECTRONIC TESTING, vol. 24, pp. 35-44. - ISSN 0923-8174
Web of Science: 6 - Scopus: 10

Articolo di rivista Sterpone L; Violante M. (2008)
A new Algorithm for the Analysis of the MCUs Sensitiveness of TMR Architectures in SRAM-based FPGAs. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 55, pp. 2019-2027. - ISSN 0018-9499
Web of Science: 12 - Scopus: 13

Articolo in atti di convegno Battezzati N; Sterpone L.; Violante M (2008)
A new low-cost non intrusive platform for injecting soft errors in SRAM-based FPGAs. In: ISIE: IEEE International Symposium on Industrial Electronics, Cambridge. pp. 2282-2287
Web of Science: 0 - Scopus: 9

Articolo in atti di convegno L. Sterpone; N. Battezzati; M. Violante (2008)
A new placement algorithm for the optimization of fault tolerant circuits on reconfigurable devices. In: WREFT '08 workshop on Radiation effects and fault tolerance in nanometer technologies (ACM International Conference on Computing Frontiers), Ischia, Italy, May 5-7, 2008. pp. 347-352 [Disponibilità ristretta]
Scopus: 0
[img]

2007

Articolo in atti di convegno Sterpone L; Violante M. (2007)
An Analysis of SEU Effects in Embedded Operating Systems for Real-Time Applications. In: International Symposium on Industrial Electronics. pp. 3345-3349
Web of Science: 1 - Scopus: 5

Articolo in atti di convegno Sterpone L; Violante M (2007)
Analytical analysis of the MCUs sensitiveness of TMR architectures in SRAM-based FPGAs. In: Radiation and Its Effects on Components and Systems, 2007. RADECS 2007. 9th European Conference on.
Web of Science: 0 - Scopus: 0

Articolo in atti di convegno Manuzzato A.; Gerardin S.; Paccagnella A.; Sterpone L.; Violante M. (2007)
Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumulation in commercial SRAM-based FPGAs. In: Radiation and Its Effects on Components and Systems, 2007. RADECS 2007. 9th European Conference on.
Web of Science: 0 - Scopus: 3

Articolo di rivista Sonza Reorda M; Sterpone L; Violante M.; Lima Kastensmidt F; Carro L (2007)
Evaluating different solutions to design fault tolerant systems with SRAM-based FPGAs. In: JOURNAL OF ELECTRONIC TESTING, vol. 23, pp. 47-54. - ISSN 0923-8174
Web of Science: 10 - Scopus: 13

Articolo di rivista Sterpone L; Violante M.; Harboe Sorensen R; Merodio D; Sturesson F; Weigand R; Mattsson S (2007)
Experimental Validation of a Tool for Predicting the Effects of Soft Errors in SRAM-based FPGAs. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 6, pp. 2576-2583. - ISSN 0018-9499
Web of Science: 16 - Scopus: 21

Capitolo di libro Anghel L; Rebaudengo M; Sonza Reorda M; Violante M. (2007)
Multi-level Fault Effects Evaluation. In: Radiation Effects on Embedded Systems / R. VELAZCO; P. FOUILLAT; R. REIS. Springer, pp. 69-88. ISBN 9781402056451
Web of Science: 4 - Scopus: 5

Articolo di rivista Sterpone L; Violante M. (2007)
A New Partial Reconfiguration-based Fault-Injection System to Evaluate SEU Effects in SRAM-based FPGAs. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, pp. 965-970. - ISSN 0018-9499
Web of Science: 47 - Scopus: 73

Articolo in atti di convegno S. Pontarelli; Sterpone L.; G.C. Cardarilli; M. Re; M. Sonza Reorda; A. Salsano; M. Violante (2007)
Optimization of Self Checking FIR filters by means of Fault Injection Analysis. In: DFT, Roma. pp. 96-104
Web of Science: 0 - Scopus: 1

Articolo in atti di convegno S. Pontarelli; L. Sterpone; G.C. Cardarilli; M. Re; Sonza Reorda M.; A. Salsano; M. Violante (2007)
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. In: IOLTS2007: IEEE International On-Line Testing Symposium, Hersonissos, Greece, July 2007. pp. 194-196
Web of Science: 0 - Scopus: 1

Articolo in atti di convegno Manuzzato A; Rech P; Gerardin S; Paccagnella A; Sterpone L; Violante M. (2007)
Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs. In: International Symposium on Defect and Fault Tolerance in VLSI Systems. pp. 79-86
Web of Science: 3 - Scopus: 6

Articolo in atti di convegno Alderighi M.; Casini F.; D'Angelo S.; Mancini M.; Pastore S.; Sterpone L.; Violante M. (2007)
Soft errors in SRAM-FPGAs: A comparison of two complementary approaches. In: Radiation and Its Effects on Components and Systems, 2007. RADECS 2007. 9th European Conference on.
Web of Science: 0 - Scopus: 0

Articolo in atti di convegno Sterpone L.; M. Violante (2007)
Static and Dynamic Analysis of SEU effects in SRAM-based FPGAs. In: ETS2007: IEEE European Test Symposium, Freiburg, Germany, 2007, Freiburg, Germany, May 20-24. 2007..
Web of Science: 6 - Scopus: 8

Articolo in atti di convegno Murciano M.; Violante M (2007)
Validating the Dependability of Embedded Systems through Fault Injection by Means of Loadable Kernel Modules. In: High Level Design Validation and Test Workshop (HLDVT), Hyatt Regency Irvine, CA, USA, November 7-9, 2007. pp. 179-186
Web of Science: 2 - Scopus: 2

Articolo in atti di convegno Sterpone L.; M. Violante (2007)
A new FPGA-based edge detection system for the gridding of DNA microarray images. In: IEEE Instrumentation and Measurement Technology Conference, Warsaw, May 1-3, 2007.
Web of Science: 0 - Scopus: 3

Articolo di rivista Aguirre M. A; Baena V; Tombs J; Violante M. (2007)
A new approach to estimate the effect of single event transients in complex circuits. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, pp. 1018-1024. - ISSN 0018-9499
Web of Science: 15 - Scopus: 21

Articolo in atti di convegno Sterpone L.; M. Violante (2007)
A new decompression system for the configuration process of SRAM-based FPGAs. In: ACM 17th Great Lake Symposium on VLSI, Stresa, March 11-13, 2007.
Web of Science: 1 - Scopus: 2

Articolo in atti di convegno Sterpone L.; M. Violante (2007)
A new hardware architecture for performing the gridding of DNA microarray images. In: ACM 17th Great Lake Symposium on VLSI, Stresa, March 11-13, 2007..
Web of Science: 1 - Scopus: 2

Articolo di rivista Violante M.; Sterpone L; Manuzzato A; Gerardin S; Rech P; Bagatin M; Paccagnella A; Andreani C; Gorini G; Pietropaolo A; Cardarilli G; Pontarelli S; Frost C (2007)
A new hardware/software platform and a new 1/E neutron source for soft error studies: testing FPGAs at the ISIS facility. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, pp. 1184-1189. - ISSN 0018-9499
Web of Science: 44 - Scopus: 75

Articolo in atti di convegno Violante M., Sonza Reorda M., Sterpone L., Manuzzato A., Gerardin S., Rech P., Bagatin M., Paccagnella A., Andreani C., Gorini G., Pietropaolo A., Cardarilli G., Salsano A., Pontarelli S., Frost C. (2007)
A new hardware/software platform for the soft-error sensitivity evaluation of FPGA devices. In: 8th IEEE Latin American Test Workshop, Cuzco, Peru. pp. 1-6

Articolo in atti di convegno Abate F.; Sterpone L.; Violante M. (2007)
A new mitigation approach for soft errors in embedded processors. In: Radiation and Its Effects on Components and Systems, 2007. RADECS 2007. 9th European Conference on.
Web of Science: 0 - Scopus: 0

2006

Articolo di rivista L. Sterpone; Violante M.; S. Rezgui (2006)
An Analysis based on Fault Injection of Hardening Techniques for SRAM-based FPGAs. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, pp. 2054-2059. - ISSN 0018-9499
Web of Science: 25 - Scopus: 31

Articolo in atti di convegno M. Rebaudengo; Sterpone L.; M. Violante; C. Bolchini; A. Miele; D. Sciuto (2006)
Combined software and hardware techniques for the design of reliable IP processors. In: 21th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. pp. 265-273
Web of Science: 1 - Scopus: 7

Articolo in atti di convegno L. Sterpone; Violante M. (2006)
Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices. In: NON SPECIFICATO. pp. 189-190
Scopus: 1

Articolo di rivista J. Perez; Sonza Reorda M.; M. Violante (2006)
Early, Accurate Dependability Analysis of CAN-Based Networked Systems. In: IEEE DESIGN & TEST OF COMPUTERS, vol. 23 n. 1, pp. 38-45. - ISSN 0740-7475 [Disponibilità ristretta]
Web of Science: 6 - Scopus: 10
[img]

Articolo in atti di convegno M. Portela-Garcia; Sterpone L.; C. Lopez-Ongil; M. Sonza Reorda; M. Violante (2006)
A Fault Injection Environment for SoPC's Embedded Microprocessors. In: 7th IEEE Latin-American Test Workshop, Buenos Aires, Argentina. pp. 68-73

Articolo in atti di convegno M. Sonza Reorda; L. Sterpone; Violante M.; M. Portela-Garcia; C. Lopez-Ongil; L. Entrena (2006)
Fault Injection-based Reliability Evaluation of SoPCs. In: IEEE European Test Symposium. pp. 75-82
Web of Science: 2 - Scopus: 15

Articolo di rivista Bernardi P.; L. Sterpone; M. Violante; M. Portela-Garcia (2006)
HYBRID FAULT DETECTION TECHNIQUE A CASE STUDY ON VIRTEX-II PRO'S POWERPC. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 53, pp. 3550-3557. - ISSN 0018-9499
Web of Science: 8 - Scopus: 10

Articolo di rivista Sterpone L; Violante M. (2006)
Hardening FPGA-based systems against SEUs: A new design methodology. In: JOURNAL OF COMPUTERS, vol. 1, pp. 22-30. - ISSN 1796-203X
Scopus: 3

Articolo in atti di convegno M. Sonza Reorda; Violante M. (2006)
Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems. In: NON SPECIFICATO. pp. 229-234
Scopus: 4

Articolo in atti di convegno Lisboa C.A.L; Carro L; Reorda M.S; Violante M. (2006)
Online hardening of programs against SEUs and SETs. In: IEEE Symposium on Defect and Fault Tolerance in VLSI Systems. pp. 280-290
Web of Science: 2 - Scopus: 6

Articolo in atti di convegno L. Sterpone; Violante M. (2006)
ReCoM: A new Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications. In: IEEE Workshop Design and Diagnostic of Electronic circuits and systems. pp. 54-58
Web of Science: 0 - Scopus: 5

Articolo in atti di convegno Bernardi P.; L. Bolzani; M. Violante; M. Sonza Reorda; A. Manzone; M. Ossela (2006)
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications. In: NON SPECIFICATO.
Scopus: 2

Libro Golubeva O.; M. Rebaudengo; M. Sonza Reorda; M. Violante (2006)
Software-Implemented Hardware Fault Tolerance. Springer Science+Business Media, LLC, NEW-YORK. ISBN 9780387260600

Articolo in atti di convegno Martina M.; G. Masera; A. Molino; F. Vacca; L. Sterpone; M. Violante (2006)
A new approach to compress the configuration information of programmable devices. In: DATE, Monaco di Baviera, 6-10 marzo 2006. pp. 1289-1293
Web of Science: 0 - Scopus: 13

Articolo in atti di convegno Schillaci M.; M. Sonza Reorda; M. Violante (2006)
A new approach to cope with single event upsets in processor-based systems. In: LATW 2006, 7th IEEE Latin American Test Workshop, Buenos Aires, March 26-29 2006. pp. 145-150

Articolo di rivista Bernardi P.; Veiras Bolzani Lm.; M. Rebaudengo; M. Sonza Reorda; F.L. Vargas; M. Violante (2006)
A new hybrid fault detection technique for systems-on-a-chip. In: IEEE TRANSACTIONS ON COMPUTERS, vol. 55, pp. 185-198. - ISSN 0018-9340 [Disponibilità ristretta]
Web of Science: 38 - Scopus: 57
[img]

Articolo di rivista L. Sterpone; Violante M. (2006)
A new reliability-oriented place and route algorithm for SRAM-based FPGAs. In: IEEE TRANSACTIONS ON COMPUTERS, vol. 55 n. 6, pp. 732-744. - ISSN 0018-9340 [Disponibilità ristretta]
Web of Science: 83 - Scopus: 108
[img]

2005

Articolo di rivista L. Sterpone; Violante M. (2005)
Analysis of the robustness of the TMR architecture in SRAM-based FPGAs. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 52 n. 5, pp. 1545-1549. - ISSN 0018-9499 [Disponibilità ristretta]
Web of Science: 50 - Scopus: 70
[img]

Articolo in atti di convegno Sanchez E.; Sonza Reorda M; Squillero G; Violante M (2005)
Automatic Generation of Test Sets for SBST of Microprocessor IP Cores. In: 18th Symposium on Integrated Circuits and Systems Design, SBCCI. pp. 74-79
Web of Science: 1 - Scopus: 6

Articolo in atti di convegno M. Sonza Reorda; Sterpone L.; M. Violante (2005)
Efficient estimation of SEU effects in SRAM-based FPGAs. In: IEEE International On-Line Testing Symposium. pp. 54-59
Web of Science: 5 - Scopus: 16

Articolo in atti di convegno O. Goloubeva; M. Rebaudengo; M. Sonza Reorda; Violante M. (2005)
Improved Software-Based Processor Control-Flow Errors Detection Technique. In: The Annual Reliability and Maintainability Symposium. pp. 583-589
Web of Science: 6 - Scopus: 19

Articolo in atti di convegno M. Sonza Reorda; Sterpone L.; M. Violante (2005)
Multiple errors produced by single upsets in FPGA configuration memory: a possible solution. In: IEEE European Test Symposium. pp. 136-141
Web of Science: 9 - Scopus: 33

Articolo di rivista L. Sterpone; Violante M. (2005)
A New Analytical Approach to Estimate the Effects of SEUs in TMR Architectures Implemented Through SRAM-based FPGAs. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 52 n. 6, pp. 2217-2223. - ISSN 0018-9499 [Disponibilità ristretta]
Web of Science: 58 - Scopus: 75
[img]

Articolo in atti di convegno E. Sanchez; M. Schillaci; M. Sonza Reorda; Squillero G.; L. Sterpone; M. Violante (2005)
New Evolutionary Techniques for Test-Program Generation for Complex Microprocessor Cores. In: Genetic and Evolutionary Computation Conference. pp. 2193-2194
Web of Science: 1 - Scopus: 2

Articolo in atti di convegno P. Bernardi; L. Bolzani; M. Rebaudengo; M. Sonza Reorda; F. Vargas; Violante M.; (2005)
On-line Detection of Control-Flow Errors in SoCs by means of an Infrastructure IP core. In: IEEE Dependable Systems and Networks Symposium. pp. 50-58
Web of Science: 6 - Scopus: 12

Articolo in atti di convegno P. Bernardi; L. Bolzani; M. Rebaudengo; M. Sonza Reorda; F.L. Vargas; M. Violante (2005)
Pandora I-IP: an HW/SW approach to Control Flow Checking. In: 6th IEEE Latin American Test Workshop - LATW'05, Bahia Brazil, March 30 - April 2.

Articolo in atti di convegno L. Sterpone; M. Sonza Reorda; Violante M. (2005)
RoRA: a reliability-oriented place and route algorithm for SRAM-based FPGAs. In: NON SPECIFICATO. pp. 173-176
Web of Science: 0 - Scopus: 7

Curatela M. Sonza Reorda; Z. Peng; Violante M. (2005)
System-level Test and Validation of Hardware/Software Systems. [Curatela]

Capitolo di libro O. Golubeva; M. Sonza Reorda; Violante M. (2005)
Test Generation: A Heuristic Approach. In: System-level test and Validation of Hardware/Software Systems / M SONZA REORDA; Z. PENG; M. VIOLANTE. Springer, LONDON, pp. 47-65. ISBN 9781852338992

Articolo in atti di convegno L. Sterpone; Violante M. (2005)
A design flow for protecting FPGA-based systems against single event upsets. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. pp. 436-444
Web of Science: 6 - Scopus: 14

Articolo in atti di convegno Sterpone L., Rezgui S, Violante M (2005)
An experimental analysis of hardening techniques for SRAM-based FPGAs. In: Radiation and Its Effects on Components and Systems, 2005. RADECS 2005. 8th European Conference on.
Scopus: 2

Articolo in atti di convegno Sterpone L.; M. Violante; S. Rezgui (2005)
An experimental analysis of hardening techniques for SRAM-based FPGAs. In: RADECS. J5-1-J5-4
Scopus: 2

Articolo in atti di convegno P. Bernardi; L. Bolzani; M. Rebaudengo; M. Sonza Reorda; Violante M. (2005)
An integrated approach for increasing the soft-error detection capabilities in SoCs processors. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. pp. 307-312
Web of Science: 0 - Scopus: 3

2004

Articolo in atti di convegno O. Goloubeva; M. Sonza Reorda; Violante M. (2004)
Automatic Generation of Validation Stimuli for Application-Specific Processors. In: DATE2004: Design, Automation and Test in Europe, Feb. 16-20, 2004. pp. 188-193
Web of Science: 3 - Scopus: 5

Articolo in atti di convegno Goloubeva O.; Sonza Reorda M.; Violante M. (2004)
Automatic generation of validation stimuli for application-specific processors. In: Design, Automation and Test in Europe Conference and Exhibition. pp. 188-193
Web of Science: 3 - Scopus: 5

Articolo in atti di convegno P. Bernardi; L. Bolzani; M. Rebaudengo; M. Sonza Reorda; F.L. Vargas; M. Violante (2004)
Cerberus I-IP: an HW/SW approach to Control Flow Checking. In: 2nd IEEE International Workshop on Infrastructure IP - I-IP'04, Lisbon, Portugal, December 5-8.

Articolo di rivista M. Sonza Reorda; Violante M. (2004)
Efficient analysis of single event transients. In: JOURNAL OF SYSTEMS ARCHITECTURE, vol. 50, pp. 239-246. - ISSN 1383-7621
Web of Science: 4 - Scopus: 8

Articolo in atti di convegno M. Bellato; Bernardi P.; D. Bortolato; A. Candelori; M. Ceschia; A. Paccagnella; M. Rebaudengo; M. Sonza Reorda; M. Violante; P. Zambolin (2004)
Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA. In: Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings.
Web of Science: 26 - Scopus: 63

Articolo in atti di convegno E. Sanchez; Squillero G.; M. Violante (2004)
Exploiting HW Acceleration for Classifying Complex Test Program Generation Problems. In: EvoWorkshops 2004: EvoBIO, EvoCOMNET, EvoHOT, EvoISAP, EvoMUSART, and EvoSTOC, Coimbra, April 5-7, 2004. pp. 230-239
Web of Science: 0 - Scopus: 1

Articolo in atti di convegno L. Bolzani; M. Rebaudengo; M. Sonza Reorda; F.L. Vargas; M. Violante (2004)
Hybrid Soft Error Detection by means of Infrastructure IP cores. In: 10th IEEE International On-Line Test Symposium - IOLTS'04, Madeira Island, Portugal, Jully 12-14.
Web of Science: 0 - Scopus: 20

Articolo in atti di convegno L. Bolzani; Rebaudengo M.; M. Sonza Reorda; F. Vargas; M. Violante (2004)
An Infrastructure IP for Soft Error Detection. In: LATW'04: IEEE Latin-American Test WorkShop, Cartagena, Colombia, 8-10 marzo 2004.
Scopus: 20

Articolo in atti di convegno E. Sanchez; G. Squillero; Violante M. (2004)
A Local Analysis of the Genotype-Fitness Mapping in Hardware Optimization Problems. In: Congress on Evolutionary Computation. pp. 871-878
Web of Science: 0 - Scopus: 0

Articolo in atti di convegno P. Bernardi; M. Sonza Reorda; L. Sterpone; Violante M. (2004)
On the evaluation of SEU sensitiveness in SRAM-based FPGAs. In: IEEE International On-Line Testing Symposium. pp. 115-120
Web of Science: 28 - Scopus: 44

Articolo in atti di convegno M. Sonza Reorda; Violante M. (2004)
On-line Analysis and Perturbation of CAN Networks. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. pp. 424-432
Web of Science: 10 - Scopus: 18

Articolo di rivista M. Violante; L. Sterpone; M. Ceschia; D. Bortolato; P. Bernardi; Sonza Reorda M.; A. Paccagnella (2004)
Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. Volume: 51 , Issue: 6 , Part: 2, pp. 3354-3359. - ISSN 0018-9499 [Disponibilità ristretta]
Web of Science: 32 - Scopus: 35
[img]

Capitolo di libro O. Goloubeva; M. Rebaudengo; Sonza Reorda M.; M. Violante (2004)
Software Techniques for Dependable Computer-based Systems. In: Space radiation environment and its effects on spacecraft components and systems / R. ECOFFET. Cépaduès, TOULOUSE, pp. 461-480. ISBN 9782854286540

Articolo in atti di convegno F. Corno; J. Perez; M. Ramasso; M. Sonza Reorda; Violante M. (2004)
Validation of the dependability of CAN-based networked systems. In: IEEE High-level Design Validation and Test Workshop. pp. 161-164
Web of Science: 6 - Scopus: 6

Articolo in atti di convegno Corno F.; J. Perez; M. Ramasso; M. Sonza Reorda; M. Violante (2004)
A multi-level approach to the dependability analysis of CAN networks for automotive applications. In: International Conference Integrated Chassis Control(ICC), 10-12, Nov. 2004.

Articolo in atti di convegno Corno F.; J. Perez; M. Sonza Reorda; M. Violante (2004)
A multi-level approach to the dependability analysis of networked systems based on the CAN protocol. In: SBCCI04: IEEE Symposium on Integrated Circuits and Systems Design.
Web of Science: 4 - Scopus: 8

Articolo di rivista Rebaudengo M.; M. Sonza Reorda; M. Violante (2004)
A new approach to software-implemented fault tolerance. In: JOURNAL OF ELECTRONIC TESTING, vol. 20, pp. 433-437. - ISSN 0923-8174
Web of Science: 16 - Scopus: 20

2003

Articolo di rivista M. Rebaudengo; M. Sonza Reorda; Violante M. (2003)
Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor. In: JOURNAL OF ELECTRONIC TESTING, vol. 19, numero 5, pp. 577-584. - ISSN 0923-8174
Web of Science: 2 - Scopus: 3

Articolo in atti di convegno Rebaudengo M.; M. Sonza Reorda; M. Violante (2003)
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor. In: DATE2003: Design, Automation and Test in Europe, Monaco, Germania, 3-7 marzo 2003. pp. 602-607
Web of Science: 29 - Scopus: 49

Articolo in atti di convegno J. Perez; M. Sonza Reorda; Violante M. (2003)
Accurate Dependability Analysis of CAN-based Networked Systems. In: IEEE Symposium on Integrated Circuits and Systems Design. pp. 337-342
Web of Science: 8 - Scopus: 14

Articolo in atti di convegno Violante M.; M. Sonza Reorda (2003)
Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits. In: IEEE International On-Line Testing Symposium. pp. 101-105
Web of Science: 2 - Scopus: 21

Articolo in atti di convegno Sonza Reoda M; Violante M (2003)
Accurate and efficient analysis of single event transients in VLSI circuits. In: On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE.
Web of Science: 2 - Scopus: 21

Articolo di rivista Violante M. (2003)
Accurate single-event-transient analysis via zero-delay logic simulation. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 50, volume 6, pp. 2113-2118. - ISSN 0018-9499
Web of Science: 6 - Scopus: 13

Articolo in atti di convegno Violante, M.; Ceschia, M.; Sonza Reorda, M.; Paccagnella, A.; Bernardi, P.; Rebaudengo, M.; Bortolato, D.; Bellato, M.; Zambolin, P.; Candelori, A. (2003)
Analyzing SEU Effects in SRAM-based FPGAs. In: IOLTS2003: IEEE International On-Line Testing Symposium, Isola Kos, Grecia, 7-9 luglio 2003. pp. 119-123
Web of Science: 0 - Scopus: 9

Articolo in atti di convegno J. Perez; M. Sonza Reorda; Violante M. (2003)
Dependability Analysis of CAN Networks: an emulation-based approach. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. pp. 537-544
Web of Science: 11 - Scopus: 11

Articolo in atti di convegno A. Ammari; R. Leveugle; M. Sonza Reorda; Violante M. (2003)
Detailed comparison of dependability analyses performed at RT and gate levels. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. pp. 336-343
Web of Science: 6 - Scopus: 5

Articolo in atti di convegno M. Sonza Reorda; Violante M. (2003)
Emulation-based Analysis of Soft Errors in Deep Sub-micron Circuits. In: International Conference on Field Programmable Logic and Application. pp. 616-626
Web of Science: 0 - Scopus: 1

Articolo in atti di convegno D. Appello; P. Bernardi; A. Fudoli; Rebaudengo M.; M. Sonza Reorda; V. Tancorre; M. Violante (2003)
Exploiting programmable BIST for the diagnosis of embedded memory cores. In: ITC2003: IEEE International Test Conference, Charlotte, NC, USA, 30 settembre - 2 ottobre 2003. pp. 379-385
Web of Science: 22 - Scopus: 30

Articolo in atti di convegno O. Goloubeva; M. Sonza Reorda; Violante M. (2003)
High-level test generation for hardware testing and software validation. In: IEEE International Workshop on High Level Design Validation and Test. pp. 143-148
Web of Science: 2 - Scopus: 4

Articolo di rivista M. Ceschia; M. Violante; M. Sonza Reorda; A. Paccagnella; P. Bernardi; Rebaudengo M.; D. Bortolato; M. Bellato; P. Zambolin; A. Candelori (2003)
Identification and classification of single-event upsets in the configuration memory of sram-based fpgas. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 50, pp. 2088-2094. - ISSN 0018-9499
Scopus: 77

Articolo di rivista F. Faure; R. Velazco; M. Rebaudengo; M. Sonza Reorda; Violante M. (2003)
Impact of data cache memory on the single event upset-induced error rate of microprocessors. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 50 n. 6, pp. 2101-2106. - ISSN 0018-9499
Web of Science: 14 - Scopus: 20

Articolo di rivista P. Civera; L. Macchiarulo; M. Rebaudengo; Sonza Reorda M.; M. Violante (2003)
New Techniques for efficiently assessing reliability of SOCs. In: MICROELECTRONICS JOURNAL, vol. 34, pp. 53-61. - ISSN 0959-8324
Web of Science: 6 - Scopus: 10

Articolo in atti di convegno P. Bernardi; M. Rebaudengo; M. Sonza Reorda; M. Violante (2003)
A P1500-compatible programmable BIST approach for the test of embedded flash memories. In: Design, Automation and Test in Europe, Munich (DEU), 7 March 2003. pp. 720-725 [Disponibilità ristretta]
Web of Science: 5 - Scopus: 8
[img]

Articolo in atti di convegno Golubeva O.; Sonza Reorda M.; Violante M. (2003)
An RT-level concurrent error detection technique for data dominated systems. In: 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..
Web of Science: 0 - Scopus: 1

Articolo in atti di convegno Goubeva O.; Sonza Reorda M.; Violante M. (2003)
An RT-level concurrent error detection technique for data dominated systems. In: On-Line Testing Symposium, 2003. IOLTS 2003. 9th IEEE.
Web of Science: 0 - Scopus: 1

Articolo in atti di convegno O. Goloubeva; Rebaudengo M.; M. Sonza Reorda; M. Violante (2003)
Soft-error Detection Using Control Flow Assertions. In: DFT2003: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Cambridge (MA), USA, 3-5 novembre 2003. pp. 581-588
Web of Science: 71 - Scopus: 141

Articolo in atti di convegno Goloubeva O.; Rebaudengo M. ; Sonza Reorda M. ; Violante M. (2003)
Soft-error detection using control flow assertions. In: Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on.
Web of Science: 71 - Scopus: 141

Articolo in atti di convegno Rebaudengo M.; M. Sonza Reorda; M. Violante (2003)
A new Software-based technique for low-cost Fault-Tolerant application. In: RAMS2003: The Annual Reliability and Maintainability Symposium, Tampa (FL), USA, 27-30 gennaio 2003. pp. 25-28
Web of Science: 13 - Scopus: 33

Articolo in atti di convegno D. Appello; P. Bernardi; A. Fudoli; Rebaudengo M.; M. Sonza Reorda; V. Tancorre; M. Violante (2003)
A programmable BIST approach for the diagnosis of embedded memory cores. In: ETW03: 8th IEEE European Test Workshop (, Maastricht, Olanda, 25-28 maggio 2003. pp. 101-102

2002

Articolo in atti di convegno M. Rebaudengo; M. Sonza Reorda; M. Violante (2002)
Analysis of SEU effects in a pipelined processor. In: IOLTW2002: IEEE International On-line Testing Workshop, Bendor (FRA), 8-10 July 2002. pp. 112-116 [Disponibilità ristretta]
Web of Science: 5 - Scopus: 21
[img]

Articolo di rivista Rebaudengo M.; M. Sonza Reorda; M. Violante; B. Nicolescu; R. Velazco (2002)
Coping With SEUs/SETs in Microprocessors by means of Low-Cost Solutions: A Comparative Study. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 49, pp. 1491-1495. - ISSN 0018-9499
Scopus: 31

Articolo di rivista P. Civera; L. Macchiarulo; Rebaudengo M.; M. Sonza Reorda; M. Violante (2002)
An FPGA-based approach for speeding-up Fault Injection campaigns on safety-critical circuits. In: JOURNAL OF ELECTRONIC TESTING, vol. 18, pp. 261-271. - ISSN 0923-8174
Web of Science: 60 - Scopus: 73

Articolo in atti di convegno Sonza Reorda M.; Violante M. (2002)
Fault list compaction through static timing analysis for efficient fault injection experiments. In: Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on.
Web of Science: 10 - Scopus: 10

Articolo in atti di convegno M. Sonza Reorda; Violante M.; N. Mazzocca; S. Venticinque; A. Bobbio; G. Franceschinis (2002)
A Hierarchical Approach for Designing Dependable Systems. In: IEEE International Workshop on High Level Design Validation and Test, 27-29 Ottobre 2002. pp. 63-67
Web of Science: 0 - Scopus: 0

Articolo in atti di convegno Jervan G.; Peng Z. ; Goloubeva O. ; Reorda M.S.; Violante M. (2002)
High-level and hierarchical test sequence generation. In: High-Level Design Validation and Test Workshop, 2002. Seventh IEEE International.
Web of Science: 1 - Scopus: 24

Articolo di rivista Rebaudengo M.; Sonza Reorda M.; Violante M. (2002)
Simulation-based analysis of SEU effects on SRAM-based FPGAs. In: LECTURE NOTES IN COMPUTER SCIENCE, vol. 2438, pp. 101-116. - ISSN 0302-9743
Web of Science: 5 - Scopus: 27

Articolo in atti di convegno Rebaudengo M.; M. Sonza Reorda; M. Violante (2002)
Simulation-based analysis of SEU effects on SRAM-based FPGAs. In: FPL2002: International Conference on Field Programmable Logic and Application, Montpellier, Francia, 2-4 settembre 2002. pp. 607-615
Web of Science: 5 - Scopus: 27

Articolo in atti di convegno B. Nicolescu; R. Velazco; M. Sonza Reorda; Rebaudengo M.; M. Violante (2002)
A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and Drawbacks. In: SBCCI: 15th IEEE Symposium on Integrated Circuits and Systems Design, Porto Alegre, Brasile, 9-12 settembre 2002. pp. 101-106
Web of Science: 8 - Scopus: 19

Articolo in atti di convegno Rebaudengo M.; M. Sonza Reorda; M. Violante (2002)
A new approach to software-implemented fault tolerance. In: LATW2002: IEEE Latin American Test Workshop, Montevideo, Uruguay, 10-13 febbario 2002.

Articolo in atti di convegno Rebaudengo M.; M. Sonza Reorda; M. Violante (2002)
A new functional fault model for FPGA Application-Oriented testing. In: DFT2002: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Vancouver, Canada, 6-8 novembre 2002. pp. 372-380
Web of Science: 18 - Scopus: 26

Articolo in atti di convegno Civera P.; L. Macchiarulo; M. Violante (2002)
A simplified gate-level fault model for crosstalk effects analysis. In: Defect and Fault Tolerance in VLSI Systems, 2002 (DFT 2002). pp. 31-39
Web of Science: 1 - Scopus: 1

2001

Articolo in atti di convegno Rebaudengo M.; Sonza Reorda M.; Violante M.; Nicolescu B.; Velasco R. (2001)
Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparison study. In: 6th European Conference on Radiation and Its Effects on Components and Systems.
Web of Science: 0

Articolo di rivista P. Civera; L. Macchiarulo; Rebaudengo M.; M. Sonza Reorda; M. Violante (2001)
Exploiting Circuit Emulation for Fast Hardness Evaluation. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 48, pp. 2210-2216. - ISSN 0018-9499
Web of Science: 56 - Scopus: 67

Articolo in atti di convegno P.L. Civera; L. Macchiarulo; Rebaudengo M.; M. Sonza Reorda; M. Violante (2001)
Exploiting FPGA for accelerating Fault Injection Experiments. In: IOLTW, IEEE On-Line Testing Workshop, Taormina, Italia, 9-11 luglio 2001. pp. 9-13
Web of Science: 11

Articolo in atti di convegno P.L. Civera; L. Macchiarulo; Rebaudengo M.; M. Sonza Reorda; M. Violante (2001)
Exploiting FPGA-based Techniques for Fault Injection Campaigns on VLSI Circuits. In: DFT, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, San Francisco (CA), USA, 24-26 ottobre 2001. pp. 250-258
Web of Science: 24 - Scopus: 38

Articolo in atti di convegno P.L. Civera; L. Macchiarulo; M. Rebaudengo M.; M. Sonza Reorda; M. Violante (2001)
FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. In: Field-Programmable Logic and Applications 11th International Conference, FPL 2001, Belfast (GBR), Aug. 27-29, 2001. pp. 493-502 [Disponibilità ristretta]
Scopus: 3
[img]

Articolo in atti di convegno P.L. Civera; L. Macchiarulo; Rebaudengo M.; M. Sonza Reorda; M. Violante (2001)
FPGA-based Fault Injection for Microprocessor Systems. In: ATS, IEEE Asian Test Symposium, Kyoto, Giappone, 19-21 novembre 2001. pp. 304-309
Web of Science: 8 - Scopus: 18

Articolo in atti di convegno Corno F; Sonza Reorda M; Violante M; Squillero G. (2001)
On the Test of Microprocessor IP Cores. In: DATE2001: IEEE Design, Automation & Test in Europe Conference, Munich (Germany). pp. 209-213
Web of Science: 29 - Scopus: 56

Articolo in atti di convegno Rebaudengo M.; M. Sonza Reorda; M. Violante; P. Cheynet; B. Nicolescu; R. Velazco (2001)
System Safety through Automatic High-level Code Transformations: an Experimental Evaluation. In: DATE: IEEE Design, Automation & Test in Europe Conference, Monaco, Germania, 13-16 marzo 2001. pp. 297-301
Web of Science: 4 - Scopus: 10

Articolo in atti di convegno Rebaudengo, Maurizio; Sonza Reorda Matteo; Torchiano, Marco; Violante, Massimo (2001)
A source-to-source compiler for generating dependable software. In: First IEEE International Workshop on Source Code Analysis and Manipulation, SCAM, Firenze, Italia, November 10. pp. 33-42
Web of Science: 25 - Scopus: 60

2000

Articolo in atti di convegno M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante (2000)
Automatic Test Bench Generation for Simulation-based Validation. In: Hardware/Software Codesign, 2000. CODES 2000. Proceedings of the Eighth International Workshop on, San Diego, CA, USA, 5 May 2000. pp. 136-140

Articolo in atti di convegno M. Lajolo; M. Rebaudengo; M. Sonza-Reorda; M. Violante; Lavagno L. (2000)
Behavioral-level test vector generation for system-on-chip designs. In: NON SPECIFICATO.
Web of Science: 8 - Scopus: 14

Articolo in atti di convegno Corno F; Sonza Reorda M; Squillero G.; Violante M (2000)
CA-CSTP: A new BIST Architecture for Sequential Circuit. In: ETW. pp. 167-172
Web of Science: 1

Articolo in atti di convegno M. Lajolo; L. Lavagno; M. Sonza Reorda; M. Violante (2000)
Early Power Estimation for System-on-Chip Designs. In: Power and Timing Modeling, Optimization and Simulation 10th International Workshop, PATMOS 2000, Göttingen (DEU), Sep. 13-15, 2000. pp. 108-117 [Disponibilità ristretta]
Web of Science: 0 - Scopus: 0
[img]

Articolo in atti di convegno M. Lajolo; M. Rebaudengo; M. Sonza-Reorda; M. Violante; Lavagno L. (2000)
Evaluating system dependability in a co-design framework. In: NON SPECIFICATO.
Scopus: 6

Articolo in atti di convegno M. Rebaudengo; M. Sonza Reorda; M. Violante; P. Cheynet; B. Nicolescu; R. Velazco (2000)
Evaluating the effectiveness of a Software Fault-Tolerance technique on RISC- and CISC-based architectures. In: On-Line Testing Workshop, 2000. Proceedings. 6th IEEE International, Palma de Mallorca, E, 03-05 Jul 2000. pp. 17-21
Web of Science: 2 - Scopus: 7

Articolo di rivista P. Cheynet; B. Nicolescu; R. Velazco; Rebaudengo M.; M. Sonza Reorda; M. Violante (2000)
Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 47, pp. 2231-2236. - ISSN 0018-9499
Web of Science: 54 - Scopus: 77

Articolo in atti di convegno Corno F.; M. Sonza Reorda; G. Squillero; M. Violante (2000)
A Genetic Algorithm-based System for Generating Test Programs for Microprocessor IP Cores. In: International Conference on Tools with Artificial Intelligence, Vancouver, Canada, November 13-15, 2000. pp. 195-198
Web of Science: 3 - Scopus: 8

Articolo in atti di convegno Corno F.; M. Rebaudengo; M. Sonza Reorda; G. Squillero; M. Violante (2000)
Low Power BIST via Hybrid Cellular Automata. In: VLSI Test Symposium, Montreal, Canada, May 2000. pp. 29-34
Scopus: 65

Articolo in atti di convegno Corno F; Rebaudengo M; Sonza Reorda M; Squillero G.; Violante M (2000)
Low Power BIST via Non-Linear Hybrid Cellular Automata. In: VTS. pp. 29-34
Scopus: 65

Articolo in atti di convegno B. Parrotta; M. Rebaudengo; M. Sonza Reorda; M. Violante (2000)
New Techniques for Accelerating Fault Injection in VHDL descriptions. In: On-Line Testing Workshop, 2000. Proceedings. 6th IEEE International, Palma de Mallorca, 3 - 5 Jul 2000. pp. 61-66
Web of Science: 12 - Scopus: 43

Articolo in atti di convegno F. Corno; M. Rebaudengo; M. Sonza Reorda; M. Violante (2000)
Prediction of Power Requirements for High-Speed Circuits. In: EvoWorkshops 2000: EvoIASP, EvoSCONDI, EvoTel, EvoSTIM, EvoRob, and EvoFlight, Edinburgh (GBR), April 17, 2000. pp. 247-254 [Disponibilità ristretta]
Web of Science: 0 - Scopus: 0
[img]

Articolo in atti di convegno B. Parrotta; M. Rebaudengo; M. Sonza Reorda; M. Violante (2000)
Speeding-up Fault Injection Campaigns in VHDL models. In: Computer Safety, Reliability and Security 19th International Conference, SAFECOMP 2000, Rotterdam (NLD), October 24–27, 2000. pp. 27-36 [Disponibilità ristretta]
Web of Science: 1 - Scopus: 3
[img]

Articolo in atti di convegno M. Lajolo; M. Rebaudengo; M. Sonza-Reorda; M. Violante; Lavagno L. (2000)
System-level test bench generation in a co-design framework. In: NON SPECIFICATO.
Web of Science: 0

Articolo in atti di convegno Rebaudengo M.; Sonza Reorda M.; Torchiano M.; Violante M. (2000)
An experimental evaluation of the effectiveness of automatic rule-based transformations for safety-critical applications. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. pp. 257-265
Web of Science: 8 - Scopus: 9

1999

Articolo in atti di convegno F. Corno; M. Rebaudengo; M. Sonza Reorda; M. Violante (1999)
ALPS: a peak power estimation tool for sequential circuits. In: VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on. pp. 350-353
Web of Science: 1 - Scopus: 3

Articolo in atti di convegno F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante (1999)
A New BIST Architecture for Low Power Circuits. In: European Test Workshop 1999. Proceedings, Constance, Germany, 25-28 May 1999. pp. 160-164
Scopus: 27

Articolo in atti di convegno F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante (1999)
Optimal vector selection for low power BIST. In: Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on, Albuquerque, NM, USA, Nov 1999. pp. 219-226
Scopus: 15

Articolo in atti di convegno M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante (1999)
Soft-error detection through software fault-tolerance techniques. In: IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'99), Albuquerque, NM (USA), 1-3 Nov. 1999. pp. 210-218 [Disponibilità ristretta]
Scopus: 104
[img]

Articolo di rivista F. Corno; P. Prinetto; M. Sonza Reorda; Violante M.; U. Glaeser; H.T. Vierhaus (1999)
SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information. In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 18 n. 2, pp. 191-202. - ISSN 0278-0070
Web of Science: 4 - Scopus: 4

Articolo in atti di convegno Corno F., Rebaudengo M., Sonza Reorda M., Violante M. (1999)
Test Pattern Generation under Low Power Constraints. In: 1st European Workshops, EvoIASP'99 and EuroEcTel'99, Göteborg (SWE), May 26-27, 1999. pp. 162-170 [Disponibilità ristretta]
Scopus: 0
[img]

Articolo in atti di convegno F. Corno; M. Rebaudengo; M. Sonza Reorda; M. Violante (1999)
Transformation-based peak power reduction for test sequences. In: Low-Power Design, 1999. Proceedings. IEEE Alessandro Volta Memorial Workshop on, Como, I, 4-5 Mar 1999. pp. 78-83
Web of Science: 0 - Scopus: 2

1998

Articolo in atti di convegno Corno F.; Prinetto P.; Sonza Reorda M.; Violante M. (1998)
Exploiting symbolic techniques for partial scan flip flop selection. In: DATE 1998 : IEEE Design Automation and Test Conference in Europe, 1998, Paris (France), Feb 23-26, 1998. pp. 670-679
Web of Science: 4 - Scopus: 5

Articolo in atti di convegno A. Benso; P.L. Civera; M. Rebaudengo; M. Sonza Reorda; A. Ferro; L. Macchiarulo; M. Violante; P. Prinetto; R. Ubar; J. Raik (1998)
A Hybrid Fault Injection Methodology for Real Time Systems. In: FTCS-28: 28th Annual International Symposium on Fault-Tolerant Computing, Munich (Germany), Jun 23-25, 1998. pp. 74-75

1997

Articolo in atti di convegno F. Corno; P. Prinetto; M. Rebaudengo; M. Sonza Reorda; M. Violante (1997)
Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG. In: Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian, Akita, J, 17-19 Nov 1997. pp. 68-73
Web of Science: 0 - Scopus: 1

Questa lista è stata generata il Wed Feb 21 03:12:04 2018 CET.