Test Pattern Generation under Low Power Constraints

Item Type: Proceeding
MIUR type: Proceedings > Proceedings
Title: Test Pattern Generation under Low Power Constraints
Authors string: Corno F., Rebaudengo M., Sonza Reorda M., Violante M.
University authors:
Page Range: pp. 162-170
Referee type: Not specified type
Publisher: Springer
ISBN: 3540658378
ISSN: 0302-9743
Volume: 1596
Event Title: 1st European Workshops, EvoIASP'99 and EuroEcTel'99
Event Location: Göteborg (SWE)
Event Dates: May 26-27, 1999
Abstract: A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunication systems, make power management during test a critical problem. A Genetic Algorithm computes a set of redundant test sequences, then a genetic optimization algorithm selects the optimal subset of sequences able to reduce the consumed power, without reducing the fault coverage. Experimental results gathered on benchmark circuits show that our approach decreases the peak power consumption by 20% on the average with respect to the original test sequence generated ignoring the power dissipation problem, without affecting the fault coverage
Date: 1999
Status: Published
Language of publication: English
Uncontrolled Keywords:
Departments (original): UNSPECIFIED
Departments: DAUIN - Department of Control and Computer Engineering
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    Date Deposited: 13 Oct 2010 23:10
    Last modification data (IRIS): 22 Jan 2013 15:01:09
    Update date (PORTO): 28 Oct 2014 12:57
    Id Number (DOI): 10.1007/10704703_13
    Permalink: http://porto.polito.it/id/eprint/2374690
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