A parallel genetic algorithm for Automatic Generation of Test Sequences for digital circuits

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Item Type: Proceeding
MIUR type: Proceedings > Proceedings
Title: A parallel genetic algorithm for Automatic Generation of Test Sequences for digital circuits
Authors string: Corno F., Prinetto P., Rebaudengo M., Sonza Reorda M.
University authors:
Page Range: pp. 454-459
Referee type: Not specified type
Publisher: Springer
ISBN: 3540611428
ISSN: 0302-9743
Volume: 1067
Event Title: High-Performance Computing and Networking International Conference and Exhibition HPCN EUROPE 1996
Event Location: Brussels (BEL)
Event Dates: April 15–19, 1996
Abstract: The paper deals with the problem of Automatic Generation of Test Sequences for digital circuits. Genetic Algorithms have been successfully proposed to solve this industrially critical problem; however, they have some drawbacks, e.g., they are often unable to detect some hard to test faults, and require a careful tuning of the algorithm parameters. In this paper, we describe a new parallel version of an existing GA-based ATPG, which exploits competing sub-populations to overcome these problems. The new approach has been implemented in the PVM environment and has been evaluated on a workstation network using some of the standard benchmark circuits. The results show that it is able to significantly improve the results quality (by testing some critical faults) at the expense of increased CPU time requirements
Date: 1996
Status: Published
Language of publication: English
Uncontrolled Keywords:
Departments (original): UNSPECIFIED
Departments: DAUIN - Department of Control and Computer Engineering
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    Date Deposited: 13 Oct 2010 23:22
    Last modification data (IRIS): 25 Nov 2013 11:53:17
    Update date (PORTO): 28 Oct 2014 12:57
    Id Number (DOI): 10.1007/3-540-61142-8_583
    Permalink: http://porto.polito.it/id/eprint/2374694
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