Pubblicazioni dell'autore: Andrea Calimera [Rubrica]

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Vai a: 2016 | 2015 | 2014 | 2013 | 2012 | 2011 | 2010 | 2009 | 2008 | 2007
Numero di pubblicazioni : 76.

2016

Articolo in atti di convegno Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2016)
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies. In: 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montreal's Sheraton Centre, can, 2016. p. 2897
Web of Science: 0 - Scopus: 0

Articolo in atti di convegno Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2016)
Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture. In: 26th ACM Great Lakes Symposium on VLSI, GLSVLSI 2016, usa, 2016. pp. 145-150
Web of Science: 0 - Scopus: 1

Articolo in atti di convegno Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2016)
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits. In: 24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallin, Estonia, 26-28 Settembre 2016. pp. 1-6
Web of Science: 0 - Scopus: 0

Articolo di rivista Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2016)
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs. In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS. - ISSN 1549-7747
Web of Science: 0 - Scopus: 0

Articolo in atti di convegno Peluso, Valentino; Calimera, Andrea; Macii, Enrico; Alioto, Massimo (2016)
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs. In: 24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallin (Estonia), 2016. pp. 1-6
Web of Science: 0 - Scopus: 0

2015

Articolo in atti di convegno Jahier Pagliari, Daniele; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2015)
An Automated Design Flow for Approximate Circuits based on Reduced Precision Redundancy. In: 33rd IEEE International Conference on Computer Design (ICCD), New York City (USA), 18-22 Ottobre 2015. pp. 86-93
Web of Science: 0 - Scopus: 0

Articolo in atti di convegno Chen, Yukai; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2015)
Characterizing the Activity Factor in NBTI Aging Models for Embedded Cores. In: Great Lakes Symposium on VLSI, Pittsburgh, Pennsylvania, USA, 20-22 Maggio 2015. pp. 75-78
Scopus: 1

Articolo in atti di convegno Rizzo, Roberto Giorgio; Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2015)
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. In: GLSVLSI '15, Pittsburgh, PA (USA), 20-22 May. pp. 253-258
Scopus: 1

Articolo in atti di convegno Miryala, Sandeep; Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo; Amarú, Luca; De Micheli, Giovanni; Gaillardon, Pierre-Emmanuel (2015)
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. In: Great Lakes Symposium on VLSI. pp. 39-44 [Disponibilità ristretta]
Scopus: 3
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Articolo in atti di convegno Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2015)
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits. In: 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015, usa, 2015. pp. 1-6 [Disponibilità ristretta]
Web of Science: 0 - Scopus: 6
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Articolo di rivista Miryala, Sandeep; Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2015)
Ultra-low power circuits using graphene p-n junctions and adiabatic computing. In: MICROPROCESSORS AND MICROSYSTEMS, vol. 39 n. 8, pp. 962-972. - ISSN 0141-9331
Web of Science: 2 - Scopus: 0
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2014

Articolo di rivista Calimera A.; Loghi M.; Macii E.; Poncino M. (2014)
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches. In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 33 n. 2, pp. 251-264. - ISSN 0278-0070
Web of Science: 1 - Scopus: 3

Articolo di rivista S. Miryala.; M. Oleiro; L. Bolzani Pohls; A. Calimera; E. Macii; M. Poncino; (2014)
Modeling of Physical Defects in PN-Junction Based Graphene Devices. In: JOURNAL OF ELECTRONIC TESTING, vol. 30 n. 3, pp. 357-370. - ISSN 0923-8174
Web of Science: 1 - Scopus: 1

Articolo in atti di convegno Tenace V.; Calimera A.; Macii E.; Poncino M. (2014)
Pass-XNOR Logic: A new Logic Style for P-N Junction based Graphene Circuits. In: DATE-14: ACM/IEEE Design, Automation and Test in Europe.
Web of Science: 0 - Scopus: 9

Articolo in atti di convegno V. Tenace; A. Calimera; E. Macii; M. Poncino (2014)
Quantifying the figures of merit of graphene-based adiabatic Pass-XNOR Logic (PXL) circuits. In: PRIME-14: IEEE Conference on Ph.D. Research in Microelectronics and Electronics. pp. 1-4
Web of Science: 0 - Scopus: 2

Articolo di rivista Tenace V.; Miryala S.; Calimera A.; Macii A.; Macii E.; Poncino M. (2014)
Row-Based Body-Bias Assignment for Dynamic Thermal Clock-Skew Compensation. In: MICROELECTRONICS JOURNAL, vol. 45 n. 5, pp. 530-538. - ISSN 0959-8324
Web of Science: 0 - Scopus: 0

Articolo in atti di convegno S. Miryala; A. Calimera; E. Macii; M. Poncino (2014)
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates. In: DSD-14: IEEE Euromicro Conference on Digital System Design. pp. 365-371
Web of Science: 6 - Scopus: 7

2013

Articolo in atti di convegno Miryala S.; Calimera A.; Macii E.; Poncino M. (2013)
Delay model for reconfigurable logic gates based on graphene PN-junctions. In: GLSVLSI-13: ACM Great Lakes Symposium on VLSI, Paris, May. pp. 227-232
Scopus: 11

Articolo in atti di convegno Calimera A.; Macii E.; Poncino M. (2013)
Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints. In: DAC-13: ACM Design Automation Conference, Austin, June. pp. 1-6
Web of Science: 0 - Scopus: 0

Articolo in atti di convegno Miryala S.; Calimera A.; Macii E.; Poncino M. (2013)
Exploration of different implementation styles for graphene-based reconfigurable gates. In: ICICDT-13: IEEE International Conference on IC Design & Technology, Pavia, May. pp. 21-24
Web of Science: 5 - Scopus: 8

Articolo di rivista Calimera A.; Macii E.; Poncino M. (2013)
The Human Brain Project and Neuromorphic computing. In: FUNCTIONAL NEUROLOGY, vol. 28 n. 3, pp. 191-196. - ISSN 0393-5264
Scopus: 19

Articolo in atti di convegno Miryala S.; Calimera A.; Macii E.; Poncino M.; Bolzani L. (2013)
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices. In: LATW-13: IEEE Latin American Test Workshop, Cordoba, April. pp. 1-6
Web of Science: 0 - Scopus: 3

Articolo di rivista Wei L.; Calimera A.; Macii A.; Macii E.; Nannarelli A.; Poncino M. (2013)
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization. In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 32 n. 3, pp. 406-418. - ISSN 0278-0070 [Disponibilità ristretta]
Web of Science: 2 - Scopus: 3
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Articolo di rivista Sassone A.; Liu W.; Calimera A.; Macii A.; Macii E.; Poncino M. (2013)
Modeling and Characterization of Thermally-Induced Skew on Clock Distribution Networks of Nanometric ICs. In: MICROELECTRONICS JOURNAL, vol. 44 n. 11, pp. 970-976. - ISSN 0959-8324
Web of Science: 5 - Scopus: 6

Articolo in atti di convegno Karimiyan Alidash H.; Calimera A.; Macii E.; Poncino M.; Macii A. (2013)
On-Chip NBTI and PBTI Tracking Through an All-Digital Aging Monitor Architecture. In: 22nd International Workshop, PATMOS, September 4-6, 2012, Newcastle upon Tyne, UK. pp. 155-165
Web of Science: 0 - Scopus: 1

Articolo in atti di convegno Miryala S.; Calimera A.; Macii E.; Poncino M. (2013)
Power Modeling and Characterization of Graphene-Based Logic Gates. In: PATMOS-13: IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation, Karlsruhe, September. pp. 223-226
Web of Science: 6 - Scopus: 7

Articolo in atti di convegno Lavratti F.; Bolzani L.; Calimera A.; Vargas F.; Macii E. (2013)
Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs. In: LATW-13: IEEE Latin American Test Workshop, Cordoba, April. pp. 1-6
Web of Science: 0 - Scopus: 3

Articolo in atti di convegno Miryala S.; Montazeri M.; Calimera A.; Macii E.; Poncino M. (2013)
A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions. In: DATE-13: ACM/IEEE Design, Automation & Test in Europe, Dresden, March. pp. 877-880
Scopus: 11

2012

Articolo di rivista Calimera A.; Macii A.; Macii E.; Poncino M. (2012)
Design Techniques and Architectures for Low-Leakage SRAMs. In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS, vol. 59 n. 9, pp. 1992-2007. - ISSN 1549-8328 [Disponibilità ristretta]
Web of Science: 11 - Scopus: 25
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Articolo di rivista Calimera A.; Macii E.; Poncino M. (2012)
Design Techniques for NBTI-Tolerant Power-Gating Architectures. In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS, pp. 249-253. - ISSN 1549-7747
Web of Science: 8 - Scopus: 14

Articolo in atti di convegno Loghi M., Mahmood H, Calimera A., Poncino M., Macii E. (2012)
Energy-optimal caches with guaranteed lifetime. In: ISLPED '12; ACM/IEEE International Symposium on Low Power Electronics and Design, Redondo Beach, California, August, 2012. pp. 141-146
Scopus: 2

Articolo in atti di convegno Miryala S., Calimera A., Macii E., Poncino M. (2012)
IR-Drop Analysis of Graphene-Based Power Distribution Networks. In: DATE-12: IEEE Design Automation and Test in Europe, Dresden, Germany, March 2012. pp. 81-86
Scopus: 0

Articolo in atti di convegno Sassone A., Calimera A., Macii A.; Macii E., Poncino M., Goldman R., Melikyan V., Babayan E., Rinaudo S. (2012)
Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, Dresden, Germany, March 2012. pp. 165-166
Scopus: 5

Articolo in atti di convegno Tenace V.; Miryala S.; Calimera A.; Macii A.; Macii E.; Poncino M. (2012)
Layout Constrained Body-Biasing for Temperature Induced Clock-Skew Compensation. In: THERMINIC-12: IEEE International Workshop on Thermal Investigations of ICs and Systems, Budapest, September. pp. 1-6

Articolo in atti di convegno Wei L., Miryala S., Tenace V., Calimera A., Macii E., Poncino M. (2012)
NBTI effects on tree-like clock distribution networks. In: GLSVLSI-12: IEEE/ACM Great Lakes symposium on VLSI, Salt Lake City, Utah, May 2012. pp. 279-282
Scopus: 2

Articolo di rivista Ferri C.; Papagiannopoulou D.; Bahar R.I.; Calimera A. (2012)
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems. In: JOURNAL OF ELECTRONIC TESTING, vol. 28 n. 3, pp. 349-363. - ISSN 0923-8174
Web of Science: 1 - Scopus: 1

Articolo di rivista Karimiyan H.; Calimera A.; Macii A.; Macii E.; Poncino M. (2012)
On-Chip PV Tracking Through an All-Digital Monitoring Architecture. In: IET CIRCUITS, DEVICES & SYSTEMS, vol. 6 n. 5, pp. 366-373. - ISSN 1751-858X
Web of Science: 1 - Scopus: 1

Articolo in atti di convegno A. Calimera, W. Liu, E. Macii, A. Nannarelli, M. Poncino (2012)
Power and Aging Characterization of Digital FIR Filters Architectures. In: 1st MEDIAN Workshop.

2011

Articolo in atti di convegno A. Calimera,M. Loghi,E. Macii,M. Poncino (2011)
Buffering of frequent accesses for reduced cache aging. In: GLS-VLSI: ACM/IEEE Great Lakes Symposium on VLSI, 2011. pp. 295-300
Scopus: 0
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Articolo in atti di convegno A. Sassone, W. Liu, A. Calimera, A. Macii, E. Macii, M. Poncino (2011)
Modeling of thermally induced skew variations in clock distribution network. In: 17th International Workshop on Thermal Investigations of ICs and Systems, THERMINIC 2011, Paris (FRA), 27-29 Sept. 2011. pp. 1-6
Scopus: 4
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Articolo in atti di convegno S. Rinaudo, G. Gangemi, A. Calimera, A. Macii, M. Poncino (2011)
Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems. In: 14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011, Grenoble (FRA), 14-18 March 2011. pp. 1127-1128 [Disponibilità ristretta]
Scopus: 0
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Articolo in atti di convegno C. Ferri,D. Papagiannopoulou,R. Bahar,A. Calimera (2011)
NBTI-Aware Data Allocation Strategies for Scratchpad Memory Based Embedded Systems. In: LATW: IEEE Latin American Test Workshop, 2011. pp. 1-6
Scopus: 15
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Articolo in atti di convegno F. Lavratti,A. Calimera,L. Bolzani,F. Vargas,E. Macii (2011)
A New Built-In Current Sensor Scheme to Detect Dynamic Faults in Nano-Scale SRAMs. In: LATW: IEEE Latin American Test Workshop, 2011. pp. 1-6
Scopus: 1
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Articolo in atti di convegno A. Calimera,M. Loghi,E. Macii,M. Poncino (2011)
Partitioned cache architectures for reduced NBTI-induced aging. In: DATE: IEEE Design, Automation and Test in Europe, 2011. pp. 1-6
Scopus: 14
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Articolo di rivista L.D. Lima;A. Calimera;A. Macii;E. Macii;M. Poncino (2011)
Power Efficient Variability Compensation Through Clustered Tunable Power-Gating. In: IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, vol. 1 n. 3, pp. 242-253. - ISSN 2156-3357
Web of Science: 3 - Scopus: 5

Articolo in atti di convegno K. Lingasubramanian; A. Calimera; A. Macii; E. Macii; M. Poncino (2011)
Sub-row sleep transistor insertion for concurrent clock-gating and power-gating. In: 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011, Madrid (SP), September 26-29, 2011. pp. 214-225 [Disponibilità ristretta]
Web of Science: 0 - Scopus: 0
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Articolo in atti di convegno H. Karimiyan;A. Calimera;A. Macii;E. Macii;M. Poncino (2011)
An on-chip all-digital PV-monitoring architecture for digital IPs. In: 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011, Madrid (SP), September 26-29, 2011. pp. 162-172 [Disponibilità ristretta]
Web of Science: 0 - Scopus: 0
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2010

Articolo in atti di convegno A. Calimera, M. Loghi, E. Macii, M. Poncino (2010)
Aging Effects of Leakage Optimizations for Caches. In: ACM/IEEE GLSVLSI-10: IEEE/ACM Great Lakes Symposium on VLSI, Providence, Rhode Island, May 2010. pp. 95-98
Scopus: 9
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Articolo in atti di convegno A. Calimera; E. Macii; M. Poncino (2010)
Analysis of NBTI-induced SNM degradation in power-gated SRAM cells. In: IEEE ISCAS-10: IEEE International Symposium on Circuits and Systems, May. pp. 785-788
Web of Science: 7 - Scopus: 17

Articolo di rivista Calimera A; Bahar R. I; Macii E.; Poncino M. (2010)
Dual-Vt Assignment Policies in ITD-Aware Synthesis. In: MICROELECTRONICS JOURNAL, vol. 41, pp. 547-553. - ISSN 0959-8324
Web of Science: 0 - Scopus: 0

Articolo in atti di convegno A. Calimera, M. Loghi, E. Macii, M. Poncino (2010)
Dynamic Indexing: Concurrent Leakage and Aging Optimizationfor Caches. In: ACM/IEEE ISLPED-10: ACM/IEEE International Symposium on Low Power Electronics and Design, Agosto. pp. 343-348
Scopus: 17

Articolo in atti di convegno Andrea Calimera; Enrico Macii; Danilo Ravotto; Ernesto Sanchez; Matteo Sonza Reorda (2010)
Generating Power-Hungry Test Programs for Power-Aware Validation of Pipelined Processors. In: 23rd annual symposium on Integrated circuits and system design, São Paulo, Brazil, September 2010. pp. 61-66
Web of Science: 1 - Scopus: 4

Articolo in atti di convegno M. Caldera, A. Calimera, A. Macii, E. Macii, M. Poncino (2010)
Minimizing temperature sensitivity of dual-Vt CMOS circuits using Simulated-Annealing on ISING-like models. In: THERMINIC-2010: IEEE International Workshop on Thermal Investigations of ICs and Systems, Barcelona (ESP), October. pp. 189-194 [Disponibilità ristretta]
Scopus: 0
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Articolo di rivista Calimera A.; Macii E.; Poncino M. (2010)
NBTI-Aware Clustered Power Gating. In: ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 3-1-3-25. - ISSN 1084-4309
Web of Science: 9 - Scopus: 18

Articolo in atti di convegno Wei L.; Calimera A.; Nannarelli A.; Macii E.; Poncino M. (2010)
On-chip Thermal Modeling Based on SPICE Simulation. In: 19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009, Delft (NL), September 9-11, 2009. pp. 66-75 [Disponibilità ristretta]
Web of Science: 0 - Scopus: 15
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Articolo in atti di convegno Liu W., Nannarelli A., Calimera A., Macii E., Poncino M. (2010)
Post-placement temperature reduction techniques. In: DATE'10: IEEE Designa, Automation and Test in Europe, Dresden, March. pp. 634-637
Web of Science: 0 - Scopus: 2

Articolo in atti di convegno A. Calimera, E. Macii, M. Poncino (2010)
Power-Gating: More Than Leakage Savings. In: IEEE PRIME-10: IEEE Conference on Ph.D. Research in Microelectronics and Electronics, Jul.. pp. 18-21
Scopus: 4
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Articolo in atti di convegno A. Calimera, A. Macii, E. Macii, S. Rinaudo, M. Poncino (2010)
THERMINATOR: Modeling, control and management of thermal effects in electronic circuits of the future. In: THERMINIC-10: International Workshop on Thermal Investigations of ICs and Systems, Barcelona, October. pp. 171-176 [Disponibilità ristretta]
Scopus: 2
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Articolo di rivista A. Calimera;R. Bahar;E. Macii;M. Poncino (2010)
Temperature-Insensitive Dual-Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence. In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 18 n. 11, pp. 1608-1620. - ISSN 1063-8210 [Disponibilità ristretta]
Web of Science: 7 - Scopus: 2
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Articolo in atti di convegno Acquaviva A., Calimera A., Macii A., Poncino M., Macii E., Giaconia M., Parrella G. (2010)
An integrated thermal estimation framework for industrial embedded platforms. In: GLSVLSI'10: Great Lakes Symposium on VLSI, Providence, Rhode Island, May 2010. pp. 293-298
Scopus: 0

Articolo in atti di convegno Andrea Acquaviva; Andrea Calimera; Alberto Macii; Massimo Poncino; Enrico Macii; Matteo Giaconia; Claudio Parrella (2010)
An integrated thermal estimation framework for industrial embedded platforms. In: ACM Great Lakes Symposium on VLSI 2010.
Scopus: 0

2009

Articolo di rivista Calimera A.; Benini L; Macii A; Macii E; Poncino M (2009)
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits. In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS, vol. 56 n. 9, pp. 1979-1993. - ISSN 1549-8328 [Disponibilità ristretta]
Web of Science: 17 - Scopus: 24
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Articolo in atti di convegno Bolzani L.; Calimera A.; Macii A.; Macii E.; Poncino M. (2009)
Enabling concurrent clock and power gating in an industrial design flow. In: Design, Automation and Test in Europe Conference and Exhibition, DATE '09, Nice (FRA), 20-24 April 2009. pp. 334-339 [Disponibilità ristretta]
Web of Science: 12 - Scopus: 21
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Articolo in atti di convegno Calimera A; Macii E.; Poncino M (2009)
NBTI-Aware Power Gating for Concurrent Leakage and Aging Optimization. In: ISLPED-09: ACM/IEEE International Symposium on Low-Power Electronics, San Francisco, CA, August 2009. pp. 127-132
Web of Science: 27 - Scopus: 59

Articolo in atti di convegno Calimera A; Macii E.; Poncino M (2009)
NBTI-Aware Sleep Transistor Design for Reliable Power-Gating. In: GLS-VLSI-09: ACM/IEEE 19th Great Lakes Symposium on VLSI, Boston, MA, May 2009. pp. 333-338
Web of Science: 8 - Scopus: 19

Articolo in atti di convegno Bozani L.; Calimera A.; Macii A.; Macii E.; Poncino M. (2009)
Placement-aware clustering for integrated clock and power gating. In: IEEE International Symposium on Circuits and Systems, ISCAS 2009, Taipei, Taiwan, 24-27 May 2009. pp. 1723-1726 [Disponibilità ristretta]
Web of Science: 2 - Scopus: 2
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Articolo in atti di convegno Upasani G., Calimera A., Macii A., Macii E., Poncino M. (2009)
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering. In: 19th International Workshop, PATMOS 2009, Delft (NLD), September 9-11, 2009,. pp. 227-236 [Disponibilità ristretta]
Scopus: 0
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2008

Articolo in atti di convegno Calimera A.; Bahar R.I; Macii E; Poncino M (2008)
Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis. In: Worshop on THERMal INvestigations of ICs and Systems, Rome, 24-26 September 2008. pp. 31-36
Web of Science: 1 - Scopus: 1

Articolo in atti di convegno Bolzani L; Calimera A; Macii A; Macii E.; Poncino M (2008)
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. In: DSD '08, 11th EUROMICRO Conference on, Parma, Italy, 3-5 Sept. 2008. pp. 298-303
Web of Science: 6 - Scopus: 16

Articolo in atti di convegno A. Sathanur; A. Calimera; A. Pullini; L. Benini; A. Macii; E. Macii; Poncino M. (2008)
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. In: ISCAS 2008, Seattle, WA, 18-21 May 2008.
Web of Science: 2 - Scopus: 4

Articolo in atti di convegno Calimera A; Benini L; Macii E. (2008)
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints. In: DATE-08: IEEE Design Automation and Test in Europe, Munich, Germany. pp. 973-978
Web of Science: 0 - Scopus: 9

Articolo in atti di convegno Calimera A; Bahar R. I; Macii E.; Poncino M (2008)
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. In: ISLPED-08: ACM/IEEE International Symposium on Low Power Electronics and Design, Bangalore, India. pp. 217-220
Scopus: 13

Articolo in atti di convegno Calimera A; Bahar R. I; Macii E.; Poncino M (2008)
Temperature-Insensitive Synthesis Using Multi-Vt Libraries. In: GLS-VLSI-08: ACM/IEEE 18th Great Lakes Symposium on VLSI, Orlando, FL. pp. 5-10
Scopus: 18

Articolo di rivista Calimera A; Duraisami K; Sathanur A; Sithambaram P; Bahar I; Macii A; Macii E.; Poncino M (2008)
Thermal-Aware Design Techniques for Nanometer CMOS Circuits. In: JOURNAL OF LOW POWER ELECTRONICS, vol. 3, pp. 374-384. - ISSN 1546-1998
Scopus: 1

2007

Articolo in atti di convegno Calimera A.; Macii A.; Pullini A.; Sathanur A.; Benini L.; Macii E.; Poncino M. (2007)
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. In: GLSVLSI-07: ACM/IEEE 17th Great Lakes Symposium on VLSI, Stresa, Marzo. pp. 501-504
Web of Science: 6 - Scopus: 13

Articolo in atti di convegno Sathanur A; Calimera A; Benini L; Macii A.; Macii E; Poncino M (2007)
Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing. In: DATE-07: IEEE Design Automation and Test in Europe, Nizza, Francia, 16-20 April 2007. pp. 1-6
Web of Science: 1 - Scopus: 19

Questa lista è stata generata il Wed Sep 20 17:38:36 2017 CEST.